Integration of novel materials and devices on silicon for future technologies

Resume : Although silicon photonics technology has demonstrated high performance optical modulators and detectors, efficient electrically pumped optical sources have remained a challenge. To date the most successful approach has been wafer bonding of compound semiconductor gain sections to silicon waveguides. Direct epitaxial growth of compound semiconductor materials on silicon has been frustrated by material lattice mismatch and incompatible thermal expansion coefficients between III–V materials and silicon leading to high-density threading dislocations. Quantum dot (QD) laser gain regions have proved to be less sensitive to defects than conventional bulk materials and quantum well structures, due to carrier localization and hence a reduced interaction with the defects. In our work, we have combined QD gain regions with the use of super-lattice defect filter layers to enable the direct epitaxial growth of telecommunications wavelength lasers on silicon substrates. Broad area lasers were fabricated by optical lithography with as-cleaved facets [1]. The measured room temperature threshold current density was 62.5 A cm-2, very similar to the best values for lasers grown on native substrates. Optical output powers as high as 105 mW were measured for a current density of 650 A cm-2. Lasing was obtained for substrate temperatures as high as 120 °C. An ageing test was carried out at 26 °C and 1.75 times threshold current for 3,100 hours, during which the output power reduced by 27.9% (26.4% in the first 500 hours). The extrapolated time to failure, defined as a doubling of threshold current, was 100,158 hours. 1. S. Chen et al., Nature Photonics doi:10.1038/nphoton.2016.21 (2016)

Resume : An integration of light emitting devices on Si-CMOS platform is one of the most important technique to realize novel high speed and low power electronics-systems. A monolithic integration of light emitting devices is more suitable for large-scale integration than a mounting of discreat elements. However, a reliable monolithic integration method is still controversial. In this paper, we succeeded a monolithic integration of Si-nMOSFETs and GaN-µLEDs by using a Si/SiO2/GaN-LED structure which enables a seamless fabrication-process of heterogeneous devices. A 2-inch-scale Si/SiO2/GaN-LED wafer was fabricated from a silicon-on-insulator substrate and a SiO2/GaN-LED substrate using surface activated wafer-bonding method. The embedded SiO2 acts as an electrical isolation layer between top-Si and GaN-LED layers. Prior to device fabrication, thermal tolerance of top-Si and GaN-LED layers was examined and maximum temperature in whole process flow was designed to be less than 900 °C for ensuring theramal torelance of an InGaN active layer. GaN-LED driving circuits composed of Si-nMOSFETs (W/L=100/10 µm) and GaN-µLEDs (30 µm□) were fabricated in this wafer using a standard CMOS process line. Electrical properties of the Si-nMOSFETs and the GaN-µLEDs were comparable to those of discrete elements fabricated as reference. Optical output of GaN-µLED was modulated by the gate voltage for evaluation of dynamic characteristics.Optical modulation bandwidths in excess of 10 MHz, which was due to the limitation of measurement system, was shown. These results indicated that the monolithic integration of Si-MOSFETs and GaN-µLEDs using Si/SiO2/GaN-LED structure was successfully achieved.

Resume : Nowadays short wavelength infrared (SWIR) imaging based on InP/InGaAs photodiodes is quite popular for uncooled camera. But, it remains expensive and only used for defense and scientific applications. Its cost comes essentially from the hybridization of photodiodes array with the read-out circuit, by the mean of an indium bump flip-chip process. So we suggest a new method of fabrication, in order to lowering the cost and providing a sustainable process to decrease the pixel pitch. A first challenge lies in molecular bonding of III-V structures on post-processed silicon wafers. The second challenge lies in 3D integrations achieved with “loop-hole” architecture in the III-V structure providing as well an interconnection to the readout circuit and circular photodiodes. These junctions are achieved after lateral zinc diffusion through via for p-type doping. But zinc diffusion and other processes have to be achieved at CMOS compatible temperature below 425°C compared to more than 500°C in standard process. The first attempts to diffuse Zn at temperature below 425°C were successful and photodiodes were fabricated; but results were erratic. The instability of InP during zinc diffusion is identified as the main origin. We will show that this behavior is due to the interaction of zinc with phosphorus, resulting in the formation of parasitic alloys. We will propose some thermodynamic explanations and solutions to stabilize InP during low temperature Zn diffusion. Finally we will present characterizations and performances of the photodiodes with the improved process.

Resume : III-V materials integration on silicon is interesting to boost the performances of integrated circuits owing to electronic and optoelectronic properties. A key point to fabricate efficient high speed electronic, optoelectronic and RF devices is to be able to form low resistive Ohmic contacts on III-V. Indeed low resistive contacts are needed to avoid device performance degradation such as low on-state current, high power dissipation or high leakage current... To form low resistance Ohmic contacts different methods could be used and/or combined: (i) high doping level in the semiconductor, (ii) inserting an interlayer between metal and heavily doped semiconductor and (iii) optimization of the interface between metal and semiconductor i.e. metal alloying. In this presentation, we will focus on getting high doping level (n and p-type) in GaAs, InAs and alloys, grown directly on Si(100) 300 mm substrates by MOCVD. The maximum n-type doping levels are 1019 cm-3, 5x1019 cm-3 and 2x1019 cm-3 for GaAs, InAs and In53Ga47As, respectively while maximum p-type doping levels are 5x1019 cm-3 and 2x1019 cm-3 for GaAs and In53Ga47As. Then, we have studied and optimized the growth conditions to form a continuous thin InAs layer (30 nm) on Si(100), GaAs and InGaAs with low surface roughnes (≤ 2nm). The low band gap of InAs should favor a low resistive contact formation. We will present and compare the contact resistivity measured by transmission line model on our materials.

Resume : In-rich AlInN alloys deposited by sputtering have been proposed as potential candidates to complement single-junction Si solar cells thanks to their tuneable direct bandgap within the visible spectral range. In this work we investigate the influence of material and device parameters (alloy composition, layer thickness and carrier lifetime, surface recombination, optical losses) on the photovoltaic characteristics of AlInN-on-silicon heterojunctions. For the electrical simulations we used the PC1D software, which was adapted to the specificities of III-nitride semiconductors. Devices based on 100 nm of n-Al38In62N (≈3×1020 cm-3) with a 2.4-eV bandgap on 500 µm p-Si, show promising results: open circuit voltage = 0.7 V, short-circuit current density = 3.4 mA/cm2, and fill factor = 76.7%, leading to a theoretical conversion efficiency of 17.7% under 1 sun of AM1.5G illumination without losses. Simulations show that for a given In content the main parameters responsible for the photoresponse degradation are the AlInN thickness, and surface recombination. Assuming an AlInN carrier lifetime approximately of 1 ps, a front/rear recombination rate of 105 cm/s, a Si resistivity of 10 Ω·cm, a Si front/rear recombination of 106cm/s, an interface diffusion of 2×1017cm-3 and no optical losses, the efficiency is reduced to 2.3% and the EQE drops to 60% at 600-950 nm spectral range, being in agreement with experimental results from n-Al38In62N on p-Si(111) junctions deposited by sputtering.

Resume : Recent advances in the theoretical and experimental studies of Ge/SiGe quantum wells structures will be presented with a focus on optical telecommunication applications. Firstly, high-speed stand-alone Ge/SiGe QW electro-absorption modulators and photodetectors will be reported. It will be followed by the presentation of different methods for engineering Ge/SiGe QW to tune the operating wavelength to 1.3 µm. Then the demonstration of a strong electro-refraction Ge/SiGe QW will be reported. This effect could be used to achieve optical modulation but requires the embedding of the QWs in a Mach-Zehnder interferometer. Finally it will be shown that these active devices can be combined with advanced passive structures using Ge-rich SiGe virtual substrate on graded buffer as a waveguide.

Resume : Vast progress in the fabrication of highly strained germanium (Ge) using a wafer-scalable micro-bridge technology [1] has given the perspective of a direct bandgap optical gain material [2] for the realisation of CMOS compatible laser sources. However, a key development step towards such a laser is the integration of a strain conserving optical cavity. Previous studies included DBR cavities with strain values of 2.5% [3] or less [4]. We present design, realisation and analysis of a novel corner cube cavity based on etched facets forming a pairs of parabolic mirrors placed at either side of the micro-bridge. The design offers intrinsic cavity Q-factors in excess of 2000, as is calculated from finite element simulations. Using optical graded GeOI [5], we achieved uniaxial strain values of 4.2%, as verified by micro-XRD calibrated Raman spectroscopy [6], and we investigated the photoluminescence (PL) at temperatures down to 20 K. [6] We evaluate the gain and loss via Fabry-Perot mode analysis and show Q-factors larger than 900 in the mid infrared regime. In conclusion, a high Q-factor cavity design compatible with the strain-engineering pattern is presented, providing a promising component for achieving lasing in tensile-strained direct bandgap Ge. [1] M. Süess, et al., Nat. Phot. v7, 488 (2013) [2] R. Geiger, et al., arXiv:1603.03454 [3] Petykiewicz, et al., Nano Lett., 16, 2168 (2016) [4] A. Gassenq, et al., Optical Society of America, 2015, paper CB_11_1 [5] V. Reboud, et al., Proc. SPIE 936714, 1–6 (2015) [6] A. Gassenq, et al., arXiv:1604.04391

Resume : The development of room-temperature short-wavelength infrared Si photodetectors is of paramount importance for optical communications, integrated photonics, sensing and medical imaging applications [1]. The typical peak photoresponse of conventional Si photodetectors is between 700 and 900 nm, which is mainly limited by the 1.12 eV-Si indirect band gap. Nevertheless, such intrinsic material limitation can be circumvented by introducing transition metals or chalcogens into the Si band gap at concentrations far above those obtained at equilibrium conditions [1, 2]. This new class of hyperdoped materials with a donor impurity band has been postulated as a viable route to extend the Si photoresponse at the short-wavelength infrared spectral region [3]. In this work, we report on the significant room-temperature photoresponse and performance at wavelengths as long as 3100 nm as exhibited by hyperdoped Si p-n photodiodes fabricated by Se implantation followed by flash lamp annealing (FLA). The FLA approach in the millisecond range allows for a solid-phase epitaxy that has been reported to be superior to liquid-phase epitaxy induced during pulsed laser annealing [2]. The success of our devices is primarily based on the high quality of the developed n-type hyperdoped material, which is single-phase single crystal with high electrical activation, without surface segregation of Se atoms and with an optically flat surface. [1] J. P. Mailoa, A. J. Akey, C. B. Simmons, D. Hutchinson, J. Mathews, J. T. Sullivan, D. Recht, M. T. Winkler, J. S. Williams, J. M. Warrender, P. D. Persans, M. J. Aziz, and T. Buonassisi, Nat. Commun. 5, 3011 (2014). [2] S. Zhou, F. Liu, S. Prucnal, K. Gao, M. Khalid, C. Baehtz, M. Posselt, W. Skorupa, and M. Helm, Sci. Rep. 5, 8329 (2015). [3] I. Umezu, J. M. Warrender, S. Charnvanichborikarn, A. Kohno, J. S. Williams, M. Tabbal, D. G. Papazoglou, X. C.Zhang, and M. J. Aziz, J. Appl. Phys. 113, 213501 (2013). a)Corresponding author: y.berencen@hzdr.de

Resume : Integration of photonics and electronics still lacks a light source that is monolithically integrable into existing CMOS technology. Germanium is investigated as a promising candidate for the active gain medium for a laser source, since it is CMOS compatible and because of its quasi-direct band-structure. Tensile strain in Ge decreases the energy barrier between the indirect and direct conduction band valleys to facilitate carrier injection into the direct gap in Γ. We propose a top-down method to strain Ge on Si layers by nano-structured SiGe layers. The method consists of the coherent growth of SiGe on Ge. The tensile SiGe top-layer can relax when trenches are carved, thereby pulling apart the Ge in between. FEM strain simulations show that the effect of SiGe nanostructures can be stronger if their perimetral forces are exerted on a Ge membrane rather than on bulk. The enhancement of elastic energy transfer from nanostructure to the membranes can result in the fabrication of larger strained regions of Ge. We present our first µRaman results for SiGe stressors on 100 nm thick Ge suspended membranes. While the strain is still below the induction of a direct-gap transition, we can show that SiGe nanostructures fabricated on a membrane are about twice as effective in creating strain as compared to the same nanostructures created on bulk Ge.

Resume : AlInN material has been proposed as suitable candidate for photovoltaic applications due to its tunable band gap energy as function of In composition. In previous studies we successfully achieved the growth of compact 500 nm-thick Al0.38In0.62N layers directly on Si (111) substrates by RF sputtering. This low cost technique allows low temperature deposition enabling its compatibility with Si-based solar cells. The application of AlInN for this technology requires a precise control of the properties of AlInN/Si interface. In this study we investigate the effect of introducing an AlN buffer layer on the quality of the subsequent AlInN layer on Si (111). A set of 80 nm thick Al0.38In0.62N samples was deposited by sputtering using an AlN buffer layer with thickness ranging from 0 to 25 nm. X-ray diffraction measurements show the AlInN (0002) diffraction peak with wurtzite structure pointing to no phase separation. The AlN (0002) peak is also noticeable for the two samples with the highest AlN buffer layer thickness (15 and 25 nm). A reduction of the FWHM of the rocking curve around (0002) AlInN reflection occurs when introducing an AlN buffer with thickness up to 15 nm. Atomic force microscopy measurements point to a surface roughness of the samples of 1.4±0.3 nm regardless the buffer thickness. Transmittance measurements in similar structures deposited on sapphire reveal an absorption band edge around 2.2 eV, appropriate for solar-cell applications.

Resume : Germanium (Ge), the semiconductor material at the base of the first transistor, is experiencing a renaissance due to its superior properties over that of silicon. High quality Ge nanocrystals on silicon are very attractive for both electronic and optoelectronic devices. However, the relatively large lattice mismatch and thermal expansion coefficient (TEC) mismatch make it a quite challenging task to realize defect-free Ge materials on Si. Furthermore, the Ge-Si interdiffusion causes difficulty in the control of the resulting heterostructure. In this talk, we demonstrate a new technique, namely, selective epitaxy of Ge on nano-tip patterned Si (001) wafers, which enables fully coherent Ge islands. We will discuss the pattern-independent selectivity mechanism of Ge. High growth temperatures (>750°C) are required for growth selectivity but a “geometric intermixing hindrance” effect of the Si-tip wafer confines intermixing to the pedestal region. Thanks to the strain partitioning between Ge and Si tips, the thin intermixing layer has a beneficial role to prevent the formation of misfit dislocations (MDs) at the advantage of a fully elastic relaxation. Moreover, no other defects like twins or stacking faults was observed in the Ge island volume. We shall see the key enabler of this peculiar growth mode is the shape and size of the patterned Si substrate used as “seed” for the selective epitaxy. The beneficial influence of this innovative approach on optoelectronic materials properties is demonstrated by photodetection in hybrid graphene / Ge island / Si-tip nanostructures.

Resume : Over the last decade, complementary-metal-oxide-semiconductors (CMOS) compatible GeSn alloys have attracted wide attention for a high variety of applications. For both optical and electronic devices GeSn alloys enable high-level control of the band structure by carefully adjusting the Sn content. For instance, a slight doping of Sn of 2 % into Ge enhances its absorption behavior at optical telecommunication wavelengths (1.55 1.62 μm). However, to realize high-performance optical devices, the synthesis of high quality GeSn alloys on Si faces crucial challenges, such as minimizing crystalline defects and Si interdiffusion at the interface. To solve these problems, here we explore nanoheteroepitaxy as a promising approach by examining in detail the impact of various growth conditions on the structural and optical properties of GeSn islands on pre patterned Si(001) nano-pillars surrounded by SiO2 . Using molecular beam epitaxy we demonstrate that single crystalline, fully relaxed GeSn nanocrystals can be selectively grown directly on Si(001). Scanning electron microscopy, x ray diffraction and transmission electron microscopy measurements point towards 600°C as an optimized growth temperature to achieve both high selectivity and Sn contents up to 1.4 %, while at the same time suppressing Si interdiffusion. Finally, the high crystal quality of such GeSn nano islands is confirmed by room temperature photoluminescence, revealing a redshift of the bandgap energy from that of pure Ge.

Resume : For future CMOS (Complementary Metal-Oxide-Semiconductor) devices beyond 10nm technology node, III-V semiconductor such as Indium Gallium Arsenide compounds (InxGa1-xAs) is predicted to be the main candidate for high mobility n-type channel. For this, the heterogeneous combination of III–Vs and Si is an attractive option due to the compatibility with the common Si-based platform and large scale wafer processing. However, the main issue of III-V compounds integration on Si is the large lattice mismatch (fInP/Si=8.06%) which will generate the formation of crystal defects during the growth process, such as treading dislocations(TDs) stacking faults(SFs), and then degrade the device performances. In that context, we developed an epitaxial process based on selective area growth (SAG) in wide trenches(W>200nm) on an on-axis(001)-oriented Si patterned substrate. III-V heterogeneous SAG in such wide field trenches presents multiple advantages in the choice of final device such as scaled single or multi-layer channel FinFET, Gate-All-Around (GAA), but also etched vertical nanowires. The main growth challenge is to reduce defect density in the InP buffer which is used to integrate the InGaAs channel after a planarization process step. For this we make use of several approaches to improve the InP buffer crystallinity such as V-groove engineering, buffer growth conditions, and post annealing studies. As a result, we could demonstrate a strong defect density reduction in the final wide field III-V epitaxial grown InGaAs channel layer.

Resume : Vertical InAs nanowire (NW) is a promising building block for the next generation electrical and optical devices. The quality of InAs NW selective area epitaxy (SAE) on Si substrate heavily relies on the surface pre-treatment strategy. However the early stage of InAs SAE on Si (111) substrate is much less investigated. Here we report the study of the Si surface at the initial stage of the InAs growth. A contamination problem on Si (111) surface at the beginning of high yield InAs NW growth is identified by time-of-flight secondary ion mass spectrum. These contaminants form an interfacial layer in a certain chemical stoichiometry afterwards, as identified by synchrotron grazing incident X-ray diffraction and electron dispersive spectrum. Our study shows that the interfacial layer between InAs and Si substrate is crucial for the nucleation of InAs NW during SAE. High yield (99.3%) InAs NWs SAE is achieved by using a nucleation layer playing the same role in a controlled way. This study is able to shed some light on the impact of atomic configuration between non-polar Si substrate and polar III-V epi-layer on the hetero-structure nucleation.

Resume : The interest in the integration of GaAs on Si is becoming stronger each year and is guided by applications in highly active areas such as silicon-based microelectronics technologies or photovoltaic. Significant improvements have been reported for many years, thanks to selective area epitaxy of GaAs on Si substrates patterned with dielectric films. However, these layers are inappropriate for applications involving electronic transport between GaAs and Si at a large scale. To overcome these problems we have developed a technique based on the Epitaxial Lateral overgrowth on Tunnel Oxide from nano-seed (ELTOn) of micrometer scale GaAs crystals on a 0.6 nm thick SiO2 layer from nanoscale Si seeds. This method permits the integration of high quality and defect-free crystalline GaAs on Si substrate and provides active GaAs/Si heterojunctions with efficient carrier transport through the thin SiO2 layer. The nucleation from small width openings avoids the emission of misfit dislocations and the formation of antiphase domains. With this method, we have experimentally demonstrated for the first time a monolithically integrated GaAs/Si diode with high current densities of 10 kA.cm−2 for a forward bias of 3.7 V. This epitaxial technique paves the way to hybrid III–V/Si devices that are free from lattice-matching restrictions, and where silicon not only behaves as a substrate but also as an active medium.

Resume : We introduce a continuum model allowing one to tackle heteroepitaxy on silicon at laboratory time and size scales, while capturing the complex interplay between elastic and plastic relaxation. In the model, material redistribution is described by a surface-diffusion equation, and local atomic accumulation/depletion is determined by differences in chemical potential. The latter is determined based on local curvature and elastic energy, numerically computed at each step by using Finite Element Methods. A wetting term is also added, as required to properly simulate the Stransky-Krastanow growth regime. Importantly, misfit dislocations are introduced in the system on the fly, based on a suitable energetic criterium [1]: while the profile evolves in time, scans are made to individuate possible positions where the presence of a linear defect would lower the elastic energy of the system. If the search is successful, a dislocation is added and its contribution to the chemical potential is computed in further evolution. While the model is rather simple and implemented in 2D only, it seems to predict all main experimental evidence reported in the literature, namely: (a) oscillations in SiGe islands shape and aspect ratio upon insertion of dislocations [2,3] (b) accelerated growth dynamics of dislocated islands vs. coherent ones [3] (c) kinetic suppression of islanding in “two-temperature” deposition techniques [4] The present model paves the way for the development of a reliable and predictive growth simulator tackling both morphological evolution and defects’ distribution during heteroepitaxial deposition in typical industrial growth chambers. [1] F. Rovaris, R. Bergamaschini, and F. Montalenti (2016, submitted) [2] F.K. LeGoues et al., Phys. Rev. Lett. 73, 300 (1994). [3] M. Stoffel et al., Phys. Rev. B 74, 155326 (2006). [4] E. Colace et al., Appl. Phys. Lett. 72, 3175 (1998).

Resume : Performance enhancement in future integrated circuits will come from the integration of new materials into the existing silicon platform (with leading edge manufacturing plants). The electron mobility in cubic, direct bandgap III-V semiconductors is indeed several times higher than in Si. Their integration on Si substrates is not that easy due to (i) differences in thermal expansion coefficients, (ii) the polar nature of III-V alloys (Anti-Phase Boundaries, APB) and (iii) a greater than 4% lattice mismatch. The first issue can be solved by limiting the total epitaxial thickness, the second one by the use of the proper surface preparation and the right growth conditions. However, the lattice mismatch will result in high densities of threading dislocations in III-V epitaxial films on Si. We have grown thanks to Metal Organic Chemical Vapor Deposition GaAs and InP layers on 300 mm substrates with various Ge buffer thicknesses. Those buffers were used to partly or nearly fully accommodate the lattice parameter mismatch between III-Vs and Si. We have characterized those films using AFM, bow measurement, PL, CL and XRD. We have extracted the threading dislocation density (TDD) in GaAs and InP. Our films were APB-free and smooth (at least for GaAs films). The lowest TDD achieved, around 1E7 cm-2 in 300 nm thick GaAs films, was obtained for the thickest Ge buffer (1.4 µm). Further reduction of this density (in blanket films) implies accepting a larger curvature of the wafer or the cracking of the epilayers.

Resume : The Moore’s law reached to its fundamental limits, novel device structures and materials like FinFET, 3D transistors, High-k metal gate, and compound semiconductor based structures are taken in account for further scaling of CMOS devices, attributes to enhancement in speed of the devices. Ge MOS is one of them, where it offers the high mobility channel material. Generally, (100) orientation substrates are in use as it offers the low interface trap densities. The use of high mobility channel material with different orientation has been proposed in this work, which may be the cause for further enhancement in channel mobility. In this work, the (110) orientation germanium substrates were used with high-k/metal gate (HK/MG) stack for the deposition. Prior to deposition, the Ge surface was treated thermally by means of NH3 annealing. The 5 nm thick HfO2 has been deposited on surface nitrided germanium (110) by using atomic layer deposition technique. Further, the deposition of HfO2 and GeON has been verified by means of XPS. The electrical properties have been studied by forming metal gate contacts of Cr and Au bilayer over deposited films. The Ge MOS device with HfO2/GeON gate stack shows the better device properties than that of (100) orientation substrate devices in terms of interface trap density (5.5 x 1010 cm-2eV-1). Keywords: Ge MOS, HK/MG, Nitridation. Dit

Resume : It is now possible to create atomically thin regions of dopant atoms in silicon, patterned with lateral dimensions ranging from the atomic-scale (angstroms) to microns. Such structures are now being created to produce quantum electronic devices for physics research and in future will form crucial components of next generation integrated circuits and quantum information processing devices. I will report on our progress towards fabrication and characterisation of these devices. Recently we have used scanning microwave microscopy (SMM) to image atomically thin patterned phosphorus (P) structures, buried ~15 nm below the silicon surface, with lateral dimensions varying from a few microns to tens of nanometers. The buried structures are fabricated using a scanning tunneling microscope based strategy. The SMM technique is completely non-invasive and highly sensitive to the electrical properties of the atomically thin P structures, with their sheet resistance determined to be in the range of a few ksq. By combining SMM with appropriate calibration algorithms and finite element modelling we can quantify the depth of the dopant structures (~15 nm) solely using the SMM technique, as confirmed by secondary ion mass spectrometry (SIMS) calibration measurements. At this depth we obtain a lateral imaging resolution down to ~60 nm. The ability to determine depth and electrical characteristics of buried P nanostructures leads the way towards 3D imaging of nanoscale electrical devices.

Resume : 2-dimensional (2D) materials are promising for future electronic devices like FETs and low power sensors. However, their performances are often limited by contact resistance, which can be due to dimensionality effects and Schottky Barriers (SB) at the contacts. The SBs often show Fermi level pinning (FLP), which prevent us from choosing contact metals with the suitable work function to control the Schottky barrier height (SBH). Graphene has little FLP [1] while transition metal dichalcogenides (TMD) have strong FLP [2,3]. In order to understand the origin of FLP in 2D systems, it is interesting to study its chemical trends in an extreme system such as the hexagonal B, Al and Ga Nitrides (h-XN). The SBHs ϕn of top metal contacts on monolayer h-XN are calculated using supercell models and density functional theory (DFT). The Fermi level pinning factor S is calculated as the slope of the SBH against metal work function, S = dϕn/dΦM. For h-BN, we found S = 0.99, that is no pinning. This is consistent with previous work [4]. For the h-AlN and h-GaN, we calculated S = 0.64 and 0.63 respectively, with some pinning. This is still a higher value of S that in defect-free MoS2, for which S = 0.3. The reason for the chemical trends are as follows. Graphene is sp2 bonded, and there is an energy barrier separating the sp2 from the sp3 state, so that metals on graphene leave the C atoms in their sp2 state. A similar behavior is found for h-BN. BN is more stable with sp2 bonding, most metals have a physiorption interaction with h-BN. This leaves BN layers planar, and the equilibrium distances between the metal atoms and the B or N are 3.0Å to 3.5Å, with van der Waals interactions. In contrast, the h-AlN and h-GaN layers undergo buckling, with chemisorption bonds form metals and N sites. The distances between AlN/metals and GaN/metals range from 2.0Å to 2.3Å, indicating that layers are connected mainly by chemical bond. This is because GaN and AlN are more stable in the sp3 state. In the case of MoS2 and the other metal dichalcogenides, the S or Se atoms are able to overcoordinate beyond their 3-fold bonding, so the metal contact atoms form full chemical bonds to them, and there is strong Fermi level pinning. Thus, chemistry is very important, not just dimensionality. Of course in MoS2, the contacts are dominated by defects which cause stronger FLP, but the effects of defects at h-BN or h-AlN are less. 1. Giovannetti G, Khomyakov P A, Brocks G, et al. Doping graphene with metal contacts. Phys. Rev. Letts, 2008, 101(2): 026803. 2. Guo Y, Liu D, Robertson J. 3D Behavior of Schottky Barriers of 2D Transition-Metal Dichalcogenides. ACS Appl Mater Interfaces, 2015, 7(46): 25709-25715. 3. Kang J, Liu W, Sarkar D, et al. Computational study of metal contacts to monolayer transition-metal dichalcogenide semiconductors. Phys. Rev. X, 2014, 4(3): 031005. 4. Bokdam M, Brocks G, Katsnelson M I, et al. Schottky barriers at hexagonal boron nitride/metal interfaces: A first-principles study. Phys. Rev. B, 2014, 90(8): 085415.

Resume : MoS2 recently attracted high interest as a potential candidate for post-Si CMOS technology. MoS2 is unintentionally n-type doped and most of the metals exhibit a Fermi level pinning below its conduction band. Hence, only accumulation mode n-channel FETs with Schottky source/drain contacts are easily obtained with pristine MoS2. On the other hand, p-type doping under the contacts and/or tailoring of the metal/MoS2 Schottky barrier are required for efficient hole injection, in order to obtain the complementary inversion mode p-channel FETs. O2 plasma treatments have been considered for selective area p-type doping of MoS2, but the doping mechanism is still unclear. In this work, temperature-dependent electrical characterization of MoS2 FETs with source/drain contacts on pristine and O2 plasma irradiated MoS2 have been carried out, demonstrating a striking change in the transistors electrical characteristics, i.e., from n-type conduction to ambipolar behaviour. High resolution current mapping by conductive atomic force microscopy [1] shed light into the current injection mechanisms from the metal to the virgin or O2 plasma treated MoS2 surface. These local electrical measurements, combined with high resolution transmission electron microscopy, electron energy loss spectroscopy and ab-initio simulations, allowed to clarify the effect of O2 plasma functionalization under the contacts on the MoS2 transistors electrical behaviour. [1] F. Giannazzo, et al., PRB 92, 081307(R) (2015)

Resume : Resistive switching (RS) is defined as the reversible and non-volatile change of the electrical resistance of metal-insulator-metal structures upon the application of electrical stress [1]. The most straightforward implementation of RS devices, usually called “memristors”, is as Resistive Random Access Memories (ReRAM); however, their potential goes beyond this particular application. Memristive systems were demonstrated to be able to perform logical operations [2] and, in addition, they were shown to have a similar behavior than the bit-cells of the human brain (synapses) [3]. These findings suggest that memristive devices may constitute an important technological breakthrough in the near future. Here we fabricated and characterized metal/La1/3Ca3/2MnO3 memristive devices on highly doped silicon, which turn them especially suited to be integrated with standard electronics. The oxide was grown by pulsed laser deposition and the top electrode was deposited and shaped by sputtering and optical lithography, respectively. We have previously shown that different RS mechanisms coexist in these kind of devices [4], asking for a careful analysis to disentangle and control them. In the present case, we found that using current as electrical stimulus unveils an intermediate resistance state in addition to the usual high and low resistance states that are observed in standard voltage controlled experiments. Based on detailed electrical characterization (I-V curves and hysteresis switching loops, temperature dependence of the resistive states, impedance spectroscopy), we suggest that the dominant RS mechanism in these samples comes from the electrical field induced oxygen transfer between the native SiOx layer present at the manganite/silicon interface and the nearby manganite layer. We have also found that after hard electrical breakdown, our devices can be turned functional again by performing a low temperature annealing in air, suggesting the possibility of designing devices with “self healing” capability that could be activated through local power dissipation. [1] A. Sawa, Mater. Today 11, 28 (2008). [2] J.Borghetti, G. S. Snider, P. J. Kuekes, J. J. Yang, D.R. Stewart & R. S.Williams, Nature 464, 8 (2010) [3] Jo et al., Nano Lett. 10, 1297 (2010) [4] D. Rubi, F. Tesler, I. Alposta, A. Kalstein, N. Ghenzi, F. Gomez-Marlasca, M. Rozenberg, and P. Levy, App. Phys. Lett. 103, 163506 (2013); N. Ghenzi, M. J. Sánchez, D. Rubi, M. J. Rozenberg, C. Urdaniz, M. Weissman, and P. Levy, Appl. Phys. Lett 104, 183505 (2014)

Resume : The increase in dielectric constant with the reduction of the leakage current of a dielectric material has become a crucial application of the microelectronics industry to improve the performance of electronic devices. The dielectric properties and the interface effects of a dielectric material consisting of amorphous laminates of Al2O3 and TiO2 with sub-nanometer individual layer thicknesses deposited by Pulsed Laser Deposition were studied. A high dielectric constant due to the Maxwell-Wagner effect is obtained. This effect is well-known in inhomogeneous dielectrics related to an intermixing of insulating and semiconducting regions. In the case of the sub-nanometric laminates, the insulating region is the Al2O3 and the semiconducting one is TiO2. Dielectric properties of subnanometric laminate change depending on the bottom electrode and total thickness. Chemical effects at the interface with the dielectric and top and bottom electrodes play a major role in promoting the dielectric properties. Thus, the permittivity enhances by changing Si by TiN as a bottom electrode but dielectric losses become an issue. The incorporation of an insulating layer between the dielectric and the top and bottom electrodes reduces losses and leakage current, preserving the high permittivity.

Resume : Today, the physical limitations of nanoscale transistors operation, in particular the increasing of the power consumption per chip have led to the development of innovative MOS architectures. Nanowire (NW) MOSFETs are considered the most promising candidates to pursue the downscaling of MOS transistors, outperforming of triple gate FinFET architectures for sub- 7 nm technology node. [1] because of their suitability for gate‐all‐around (GAA) architecture which represents the ideal case for the electrostatic control and can ensure the further reduction of the “ultimate” transistor size [2]. Nevertheless, the current that flows through the device when it is turned on (current drive) remains low, as it is limited by the small section of the NWs. It is therefore essential not to implement a transistor on a single wire but on nanowire arrays so to combine the excellent electrostatic control with a high current level. In that context, vertical integration is a particularly attractive approach because of its 3-D character, which is more favorable to scale the contacted gate pitch i.e. scaling of the gate length and contact area [3]. The vertical NW array based transistor is much easier to manufacture, because the gate length is simply defined by the thickness of the deposited gate material [4]. Here, we present such architectures with noteworthy demonstrations both in processing (layer engineering at nanoscale, vertical integration of a short gate length), in electrical properties (high electrostatic control, low defect level, multi-Vt platform), in the architecture (CMOS inverter) and in the perspective of ultimate scaling [1] I. Ferain et al. Nature, vol. 479, p. 310–316, (2011). [2] K. J. Kuhn et al. Proceeding of IEEE International Electron Devices Meeting (IEDM), p.171-174, (2012). [3] T.H. Bao et al. Proceeding of 44th European Solid State Device Research Conference (ESSDERC), , p.102-105 (2014). [4] G. Larrieu and X.-L. Han. Nanoscale, vol. 5, p. 2437-2441, (2013).

Resume : In this paper TCAD simulations are performed to investigate the impact of composition and doping inhomogeneity on the drain current variability observed in epitaxial InGaAs channels for 3-D NAND memories [1]. The computational model simulates our three-layers vertical test vehicle, where an epitaxial InGaAs channel deposited by MOVPE is used. The cylindrical channel is 280-nm-long, 45 nm in diameter and is surrounded by three Si-gates of 50 nm, spaced apart by 30 nm SiO2. The ONO gate stack is 12-nm-thick. Ti and highly doped Si are used as drain and source contact, respectively. Simulations focus on electron/hole transport through different materials and Schottky junctions. The following aspects are also considered: 1) [In] gradient close to the junctions, as shown by TEM-EDS mapping, 2) different channel lengths and contact areas with junctions, as evidenced by TEM, 3) different doping configurations to emulate Si diffusion from the source into the channel, as expected to happen due to high temperature InGaAs deposition. Simulations successfully explained the effect of [In] drift close to the Ti drain side, leading to resistance and ID-VD shape variations as observed in our electrical measurements. Rectifying behavior is observed when InGaAs, with low [In], is in contact with Ti, resulting in high series resistance and asymmetrical ID-VD. On the other hand, Si-doping into the InGaAs can cause high level of off current, as measured in our devices. Contact and variability issues can be mitigated by the choice of proper drain materials and doping close to the junctions. The simulations also provide design guidelines to improve current conduction in our 3-D NAND memories. References: [1]: E. Capogreco, et al., IEDM 2015, p. 40

Resume : FinFETs have emerged as a cornerstone of ultimately scaled devices. By improving the electrostatic gating, they allow to improve the subthreshold slope (SS) and to overcome the short-channel effects (SCE)[1]. In the other hand, InGaAs is establishing itself as a very promising high-mobility n-channel material that permits to restrict the power consumption issue in advanced Integrated Circuits (ICs)[2]. The fins definition is a key step of the development of FinFETs especially in the case of ultimately scaled dimensions where the slightest details are critical for achieving high performance. In this work, we present the ICP-RIE patterning of sub-10 nm InGaAs fins, grown on silicon substrate, using BCl3/N2 and BCl3/SiCl4/N2 chemistries. A systematic study of the InGaAs etching process has been carried out and the effects of the different experimental conditions on the etching kinetics and quality have been revealed. The fins have been observed by Focused Ion Beam Scanning Transmission Electron Microscopy (FIB-STEM) and the sidewalls roughness and the chemical composition of the surface have been analyzed respectively by AFM using a homemade setup where the sample is tilted to allow the tip to scan the sidewalls and X-ray Photoelectron Spectroscopy (XPS). The optimized results depict sub-10 nm width fins with smooth (LER≤2 nm) and almost vertical (>80°) sidewalls. These results open the door to sub-10nm width InGaAs FinFETs on silicon. [1] R. Deshmukh, A. Khanzode, S. Kakde, and N. Shah, “Compairing FinFETs: SOI Vs Bulk: Process variability, process cost, and device performance,” in 2015 International Conference on Computer, Communication and Control (IC4), 2015, pp. 1–4. [2] J. A. del Alamo, D. A. Antoniadis, J. Lin, W. Lu, A. Vardi, and X. Zhao, “III-V MOSFETs for Future CMOS,” in 2015 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2015, pp. 1–4.

Resume : The diversification of materials in micro-optoelectronic devices is a key issue to enable further progress in this field. The monolithic heterogeneous integration of new materials on silicon, and more generally the combination on the same wafer of materials having different physic al properties is an important challenge. In the photonic field, integration of functional oxides on semiconductor platforms such as III-V or Si would open tremendous perspectives. In particular, ferroelectric oxides such as BaTiO3 (BTO) and Pb(Zr,Ti)O3 (PZT) present optical properties liable to add flexibility, agility and reconfigurability in integrated photonic systems. In this context, we will show in this contribution how epitaxy can be used to grow crystalline oxides on silicon and III-V platforms. We will in particular show that the specific properties of these heterogeneous epitaxial systems can be used for the monolithic integration of III-V based heterostructures on SrTiO3-templated Si substrates. We will also detail some ongoing works showing how oxide/semiconductor heterostructures can be used to develop new functionalities for integrated photonics, such as high-speed modulators integrated on SOI platforms (SITOGA FP7 project) and tunable emitters and non-volatile switches based on oxide/GaAs heterostructures. This work was partly founded by European Commission: project FP7-ICT-2013-11-619456 SITOGA.

Resume : Optical modulators based on Pockels effect are key components of today’s long range optical communication networks. In recent years, Silicon photonic integrated circuit (Si-PIC) became the technology of choice for short range optical connections. However, using the Pockels effect is not possible in Si-PIC: silicon does not exhibit any Pockels effect, and attempts to integrate nonlinear materials with silicon have been cumbersome. We recently reported on a novel solution to integrate barium titanate (BTO) thin films with strong Pockels coefficients of ~150pm/V onto silicon [1]. Waveguides having low propagation losses were also fabricated[2], so that integrated devices could be obtained, including ring resonators with quality factors of 20’000[3]. In this contribution, we will report on the presence of charges in the dielectric layers building the waveguide, and on their influence upon the electro-optical performance of the devices. Different layer stacks are compared, with and without silicon being present in the waveguide. The role of a thin alumina bonding layer is also highlighted. It can act as a source of charges that influence the distribution of the electric field across the device, as well as its overlap with the optical mode. We will conclude by presenting an approach that enable to unambiguously observe Pockels effect in BTO-based ring-resonators. Our results represent a major step to fully exploit the potential of combining novel materials such as ferroelectric oxides with silicon photonics, in order to enable new integrated optical functionalities. [1] Abel, S. et al. Nat. Commun. 4, 1671 (2013) [2] Eltes, F. et al., submitted to ACS Photonics (2016) [3] Abel, S. et al. J. Light. Technol. 34, 01–6 (2016)

Resume : The recent progress of electro-optical (EO) components integrated on Silicon-On-Insulator substrates is very promising for high-efficiency, high-bandwidth photonics applications. Ferroelectric BaTiO3 (BTO) shows excellent EO performance, therefore attracting interest for the fabrication of compact optical switching devices . However, achieving efficient devices is still challenging owing to one of the fundamental bottlenecks: Control of BTO orientations. In this work, we investigate how to control the BTO domain orientation and how the domain orientation influences the EO properties of the molecular-beam-epitaxial (MBE) BTO on SrTiO3(STO)-buffered Si(001) substrate. We found that changing STO thickness and post-growth annealing can result in out-of-plane (OOP) or in-plane (IP) BTO orientation according to x-ray diffraction (XRD) measurements. The orientation dependency of the EO phenomenon is characterized by bias-dependent spectroscopic ellipsometry. We demonstrate that, due to the different component strengths in the BTO Pockels tensor, aligning an external electric field vertically to the BTO orientation improves the EO efficiency in BTO. When applying an external OOP electric field, the IP 100nm BTO on Si shows effective Pockels coefficient around 35pm/V, which is comparable with LiNbO3. In addition, EO behaviors of the BTO prepared by different growth conditions will also be benchmarked with previous studies.

Resume : LixCoO2 is a very well known material as it has been used as a cathode material in rechargeable Li–ion batteries during the last decades. Recently, resistive switching (RS) phenomena have been reported for polycrystalline LixCoO2 thin films grown on highly doped silicon wafers using conducting probe atomic force microscopy [1,2]. We have fabricated metal-insulator-metal (MIM) devices based on LixCoO2 thin films grown by pulsed laser deposition on p++ Si (111) and used two-probe I-V measurements to investigate the RS behavior of the devices. In this presentation, we will present recent results concerning the effect of SiO2- and LixCoO2-layer thickness on the RS behavior of the MIM devices. In addition, we will discuss plausible explanations for the observed phenomena and correlate them with the mechanism we have proposed in [2]. Unraveling the mechanism governing these RS phenomena could lead to the usage of LixCoO2 thin films in Si-based technological applications such as resistive random access memories (RRAM) and neuromorphic systems. [1] A. Moradpour, O. Schneegans, S. Franger, A. Revcolevschi, R. Salot, P. Auban-Senzier, C. Pasquier, E. Svoukis, J. Giapintzakis, O, Dragos, V. C. Ciomaga, P. Chrétien, Adv. Mater. 23, 4141-4145 (2011) [2] V.H. Mai, A. Moradpour, P. Auban Senzier, C. Pasquier, K. Wang, M.J. Rozenberg, J. Giapintzakis, C.N. Mihailescu, C.M. Orfanidou, E. Svoukis, A. Breza, Ch. B. Lioutas, S. Franger, A. Revcolevschi, T. Maroutian, P. Lecoeur, P. Aubert, G. Agnus, R. Salot, P.A. Albouy, R. Weil, D. Alamarguy, K. March, F. Jomard, P. Chrétien, O. Schneegans, Sci. Rep. 5, 7761 (2015)

Resume : During the last decades, silicon oxy-nitride (SiOxNy) has been a deeply investigated material, since it can be employed in different areas, for its qualities and low-cost production. Its great electrical and luminescence properties mark SiOxNy as one of the most suitable materials for thin-films transistors and LED applications, respectively [1, 2]. Due to their high conductivity and suitable optical gap, nanocrystalline and amorphous SiOxNy thin films are two of the best candidates in Silicon HeteroJunction (SHJ) solar cells, as substitutes of a-Si:H in the heteroemitter stack [3, 4]. For their highly disordered and multiphase nature, SiOxNy thin layers transport properties are still debated in literature. The present contribution aims to study conduction mechanisms at the nanoscale in these thin films, focusing on the role of the nanocrystals and deposition parameters on the nanoscale electrical properties. Local conductive properties at the nanoscale have been investigated using conductive-Atomic Force Microscopy (c-AFM) mapping and local current-voltage characteristics. Our results showed that different oxygen contents and annealing process times affect sample properties, causing changes in crystallinity fraction and in electrical transport. The investigation of current flow in such highly disordered materials could help clarify their electrical transport properties, providing information on the best deposition parameters to obtain suitable materials for SHJ solar cells application. [1] S. Hwang et al, J. Korean Phys. Soc. 51 (2007): 1096 [2] R.J. Xie et al, Sci.Technol.Adv. Mater. 8, 7 (2007): 588 [3] N. Brinkmann et al, Sol. Energ. Mat. Sol. C. 108 (2013): 180 [4] M. Perani et al, J. Phys. Chem. C 119 (2015): 13907

Resume : Optical illumination of semiconductors leads to photoinduced doping. When the illumination is local and intense, the semiconductor behaves as a conductor at THz frequencies. We have used this concept to demonstrate experimentally the photo-excitation of THz localized surface plasmon polaritons (LSPPs) in flat semiconductor layers. This demonstration is realized by a patterned optical excitation of free charge carriers in thin semiconductor films using a spatial light modulator, which enables full spatial and temporal control of plasmonic resonances without the need of physically structuring the sample. This approach is also used to excite capacitively and inductively coupled LSPPs in loaded plasmonic resonators. Plasmonic resonances on structured conductors are characterized by localized complex electromagnetic fields that we can fully characterize with subwavelength photoconductive antennas and that can be used to enhance the performance of spectroscopies and sensors. We also propose the spatially structured photoinduced doping of semiconductors to dynamically generate plasmonic waveguides and circuits. Structured illumination also enables active beaming of THz radiation with planar structures and the realization of active metasurfaces.

Resume : Heavily-doped semiconductor thin films are very promising for application in plasmonics devices at mid-infrared wavelengths because the real part of their dielectric function is negative and broadly tunable in this wavelength range. In this work we investigate heavily n-type doped germanium epilayers on silicon using infrared spectroscopy, first principle calculations, pump-probe spectroscopy and DC electrical transport measurements to determine the relation between the plasma edge and the carrier density and to quantify the mid-infrared plasmon losses. We demonstrate that the screened plasma frequency can be tuned up to 2000 cm-1 (corresponding to a doping of about 9 ∙ 1019 cm-3) and that the electron scattering rate is dominated by scattering from non-polar optical phonons and with charged impurities. We also found a weak dependence of the losses and the tunability on the crystal defect density, temperature, inactivated dopant density and the optical pump wavelength in the near infrared. Our results suggest that plasmon decay times in the picosecond range can be obtained in Ge at room temperature. In order to assess the potential performance of our approach for applications, we have produced on-chip Ge nano-antennas by lithography and reactive ion etching and demonstrated a strong signal enhancement for the molecules located in the antenna hot spots. These results pave the way towards the low-cost integration of plasmonic sensing platforms into the existing silicon foundry technologies. The research leading to these results has received funding from the European Union’s Seventh Framework Programme under grant agreement no. 613055.

Resume : Independent of the type of doping, it is challenging to achieve in semiconductors an effective carrier concentration much above 10^20 /cm3. On the other hand, the successful realization of defect free n-type and p-type ultra-doped Ge layers will enable a range of devices from sensors to quantum computers. In the case of conventional doping techniques (using equilibrium processing) the maximum carrier concentration is limited by the out-diffusion of dopants, a relatively low solid solubility limit, clustering and self-compensation processes. To overcome such limitations we have utilised strong nonequilibrium process consisting of an ion beam implantation to introduce dopants into Ge and rear-side millisecond range flash lamp annealing (FLA) for recrystallization of implanted layer and dopant activation. In contrast to conventional annealing procedures, rear-side FLA leads to full recrystallization of Ge and dopant activation independent of the pre-treatment. The maximum carrier concentration is well above 10^20 /cm3 for n-type and above 10^21 /cm3 for p-type dopants. The so-fabricated n-type Ge can be used in the field of mid-infrared plasmonics which has not been accessible by group-IV semiconductors. Single crystalline n-type Ge with carrier concentrations as high as 2.2×10^20 /cm3 displays a room-temperature plasma frequency above 1850 /cm1 (?=5.4 ?m), which is the highest value ever reported for n-type Ge. In the case of Ga implanted Ge the maximum effective carrier concentration measured at 3K is 1.1×10^21 /cm3 which is two times higher than the solid solubility limit of Ga in Ge. Our p-type Ge is defect and cluster free and shows the superconductivity at Tc = 0.95 K. These results base on the successful combination of ion beam implantation followed by the novel approach consisting of millisecond range rear-FLA. This work has been partially supported by the EU 7th Framework Programme ?EAgLE? (REGPOT-CT-2013-316014).

Resume : There is a growing need for integrated biosensors that can be directly interfaced with signal conditioning circuits as well as wireless communication systems for applications in assisted living, medical diagnostics and process diagnostics (Industry 4.0). Plasmonic oscillations in metallic nanostructures like nanoantennas or nanohole arrays are highly sensitive to changes in their dielectric environment and, thus, have proven to be able to detect smallest amounts of substances in optical biosensing applications. However, external detection units for signal evaluation are typically bulky. Here, we present vertically grown Ge-on-Si photodetector layers in combination with Al nanohole arrays structured into the top metallization. The structures were fabricated using a complementary metal oxide semiconductor (CMOS)-compatible process. We present results in the photoresponse before and after surface functionalization with immunoglobin G and subsequent application of antibody A/G. The change in photoresponse in our system is the result of an interplay of the nanohole array with waveguide structures in our semiconductor heterostructures and we discuss how this interplay can be optimized to boost sensitivity and enable integrated biosensing.

Resume : Plasmonic antennas have gained large interest for various applications such as bio sensing or optical communication systems. Doped semiconductors show plasmonic behavior in the terahertz frequency regime, and can replace metals as plasmonic material. As a special feature, the plasma frequency of semiconductors is a function of doping concentration, and hence a tunable parameter. Antennas based on metals show a skin depth of only a few tens of nanometers in the RF and THz frequency regime, and their analysis can be done based on surface waves. This is due to the large negative real part of the dielectric function in this frequency range. Doped semiconductors are able to support surface waves in the THz regime, too. However, dependent on the doping level, the skin depth can be as large as the antenna thickness, and the surface wave analysis is not valid any more. To investigate the behavior of different materials of plasmonic antennas, we carry out numerical simulations of the electromagnetic field. As example, variations of the slab length of gold and germanium slab antennas with different doping are investigated. The results based on a full numerical solution of Maxwell’s Equations and the dispersion relation of the materials is calculated with a Drude model. Characteristic antenna properties such as resonance frequency of gold slab antennas in comparison to doped germanium slab antennas will be presented and advantages and disadvantages of both materials will be discussed. It is shown that the antenna resonance frequency can be tuned by doping concentration, and compact antennas can be built. Full wave effects such as skin depth and field confinement are shown.

Resume : Electron spins bound to quantum dots are promising qubits for quantum information due to their long coherence times and potential for scalability. Group IV materials such as silicon are particularly relevant for hosting electron spin qubits due to their low abundance of nuclear spins which causes decoherence. Furthermore, these materials can be isotopically purified to have zero nuclear spin leading to orders of magnitude increase in coherence times [1] . Recently, we have demonstrated the all-electrical coherent control of a single electron spin bound to a natural Si/SiGe quantum dot by electric dipole spin resonance (EDSR) in the presence of a magnetic field gradient achieving gate fidelities of ~ 99% [2,3] . The next step in these devices is to perform a two qubit gate by controlling the exchange interaction between two electron spins that have different Zeeman energies due to nearby micromagnets [4,5]. Here, we demonstrate the independent sequential readout and coherent control of two coupled electron spins in a Si/SiGe double quantum dot with resonance frequencies separated by ~1GHz. We report on recent progress in implementing a two qubit gate in this system. [1] A. M. Tyryshkin et al., Nature materials 11, 143 (2012) [2] E. Kawakami et al., Nature Nanotechnology 9, 666 (2014) [3] E. Kawakami et al., arXiv:1602.08334 (2016) [4] T. Meunier et al., Physical Review B 83, 121403 (2011) [5] M. Veldhorst et al., Nature 526, 410 (2015)

Resume : Spin transport in a semiconductor-based two-dimensional electron gas (2DEG) system has been attractive in spintronics for more than ten years. The inherent advantages of high-mobility channel and enhanced spin-orbital interaction promise for a long spin diffusion length and efficient spin manipulation, which are essential for spintronics devices application. However, the difficulty of making high-quality ferromagnetic (FM) contacts to the buried 2DEG channel in the heterostructure systems limits the potential developments in functional devices. We report on the experimental demonstration of electrical detection of spin transport in a high-mobility 2DEG system using FM Mn-germanosilicide (Mn(Si0.7Ge0.3)x) end contacts, which is the first report of spin injection and detection in the 2DEG confined in a Si/SiGe modulation doped quantum well structure (MODQW). The extracted spin diffusion length and lifetime are l_sf = 4.5 um and tau_s=16 ns at 1.9 K, respectively, which is consistent with the fact that spin lifetime is strongly dependent on the impurity density. Our results provide a promising approach for spin injection into 2DEG system in the Si-based MODQW, which may lead to innovative spintronic applications such as spin-based transistor, logic, and memory devices.

Resume : Electronic features of the Graphene (G), like the extremely high carrier mobility and lateral conduction are the most spectacular ones [1]. The Chemical Vapor Deposition (CVD) is frequently used to G growth on the metallic substrates [2]. Alternatively the G layer could be produced directly on the insulating substrate (SiC(0001)) using both vacuum decomposition [3], or CVD growth technique [4]. In this presentation the novel procedure for G-based electronic devices fabrication by means of combined photolithography, Ar+ ion sputtering and DC magnetron metal evaporation processes will be presented. Initially, the SiC(0001) substrate entirely covered by the G layer has been used. The proposed solution prevents against semiconductor surface oxidation and therefore is much more compatible with the standard semiconductor technology. The obtained results of Raman spectra, electrical and Hall measurements of the fabricated devices (the Hall sensors and structures enabling the “transfer line” measurements) demonstrate similar properties as fabricated by means of the early used procedures. In addition the novel magnetic field sensor based on the G will be presented [5]. Acknowledgment: Polish Ministry of Science and Higher Education is acknowledged for the financial support under project No 006/62/DSPB/0216. References: [1] A.H. Castro Neto, et al. Rev. Mod. Phys. 81 109 (2009). [2] T. Iwasaki, et al., Nano Lett. 11 79 (2011). [3] Y.Q. Wu, et al. Appl. Phys. Lett. 92 092102 (2008). [4] W. Strupiński, et al. Nano Lett. 11 1786 (2011). [5] S. El-Ahmar, et al. Polish Patent Office, Patent Application No. P.416781, (2016).

Resume : Magnetic nanodots (NDs) showing a high anisotropy have received much attention because of their potential application to magnetoelectronic devices. So far, we have reported a spontaneous formation of L10-ordered FePt dots with an areal density as high as ~1E11cm-2 by remote H2-plasma (H2-RP) exposure of Pt/Fe bilayers on ultrathin SiO2/c-Si without external heating and demonstrated a unique magnetic-field dependent electron transport through individual FePt dots/ultrathin SiO2 by means of a CoPtCr-coated magnetic tip of atomic force microscopy (AFM) in a contact mode. In this work, based on size-dependent magnetic properties of FePt nanodots, we have designed and fabricated double stack FePt NDs with ultrathin internal SiO2 and characterized their magnetoelectronic transport properties as a function of external maginetic field at room temperature (RT). FePt NDs with an areal density of ~4.5E11cm-2, an average dot size of ~5.0nm and a RT coercivity as small as 0.5kOe were formed firstly by H2-RP exposure of ultrathin Pt/Fe bilayers on 2nm-thick thermally-grown SiO2 layer/Si(100) without external heating. And then, very uniform coverage of the FePt NDs with a 2nm-thick SiO2 layer by a PVD method and subsequent formation of Pt/Fe bilayers were followed by H2-RP exposure for the spontaneous formation of FePt nanodots with an areal density of ~2.5E11cm-2, an average dot size of ~8.0nm and a RT coercivity of ~2.5kOe in a similar way to the 1st formation of FePt NDs. After that, Al back contact was formed to measure the electron transport through the double stack FePt NDs on ultrathin SiO2. I-V characteristics of the double stacked FePt NDs as a function of magnetic field were measured by using non-magnetic Ph-coated AFM Tip at room temperature. With an increase in magnetic field from 1.5 to 2.5kOe in the direction normal to the sample surface, the current level is increased significantly by over one order of magnitude. Then no further change in the current level was detectable by magnetic field application of 4.5kOe. In addition, such a high conductive state obtained at 2.5kOe remains almost unchanged even in 24hr after removal of external magnetic field, which implies stable magnetization of the double stack FePt NDs. Notice that, when the magnetic field of 0.5kOe was applied in the opposite direction to the 1st magnetization, the current level was decreased markedly to the initial low current level. With further increase in the magnetic field from 1.5 to 2.5kOe, the switching to the high conductive state happened. The observed resistive switching in the double stack FePt NDs can be interpreted in terms of a change in the magnetization polarity between staked FePt NDs with different coercivities.

Resume : Single electron transistors promise unrivaled efficiency, however the cost and difficulty associated with achieving stable room temperature operation have hindered their pathway to industry. Numerous novel techniques have been demonstrated showing room temperature operation, however many of these techniques require specialized fabrication techniques. Capitalizing on traditional UV lithography and the shadow edge evaporation technique provides a greater flexibility in both material choice and simplicity of fabrication and could provide an easier path to adoption. Profiting from these techniques, planar structures can be formed with incredibly high gap length vs. width aspect ratios, with direct tunnel barriers that are independent of any sticking layer materials that may be employed. Aluminum nanogap electrodes were fabricated using these techniques and were characterized by scanning electron microscopy. Gap sizes were found to be easily controlled via the deposition angle, with a minimum gap size of 6 nm. These gaps were then filled with an Al2O3 dielectric tunnel barrier as well as Pt nanoislands, both formed using the atomic layer deposition technique. TEM and AFM imaging confirmed the growth of size-controlled, well dispersed particles which reached sizes between 1.5 nm and 5 nm, before starting to aggregate. We observed an increase of the measured current after the introduction of Pt nanoparticles in the gap.