Electronic devices

Resume : To be added

Resume : In this talk, we will be presenting a revolutionary and validated (1) CMOS fab-friendly 8-inch diameter QSTTM (Quora Substrate Technology) substrates, which are scalable to 12-inch, for GaN epitaxial growth, (2) 8-inch GaN-on-QSTTM wafers with epi layer thicknesses ranging from a few m to >10 m for 100V to 1,200V and beyond power devices, and (3) QSTTM-based power device results enabling an unmatched cost, performance, and application scale. The QSTTM substrates with a compliant Si <111> growth surface have a thermal expansion coefficient that matches GaN, alleviating the fundamental difficulties which are inherent to large-diameter GaN-on-Si growth. Wafer bow during and after GaN growth is minimized, and thick epi layers (>>10um) can be grown without epi cracking. 8-inch diameter crack-free MOCVD GaN epi layers with <2 mm edge exclusion, 15 um bow, ~200 arcsec (002) / ~350 arcsec (102) FWHM, and dislocation densities of 1-4x108 cm-2 will be presented. The results from HVPE grown crack-free GaN epi layers with the thickness of >30um, 140 arcsec (002) / 150 arcsec (102), and dislocation density of <1x108 cm-2 as well as high-voltage HEMT and Schottky rectifier results will be included in the talk as well.

Resume : Commercially available GaN power devices are built on electrically conductive Si substrate. Different from the vertical Si power devices where the Si substrate is part of the drain terminal, the Si substrate in lateral GaN-on-Si power devices can be used as an independent termination port while also serves as a thermal cooling pad. Although implemented in many packaged GaN devices, it remains unclear whether the grounded substrate (GS) termination (i.e. with the substrate shorted to the source terminal) is the optimum choice in view of the devices’ dynamic performance. Meanwhile, a floating substrate (FS) termination could result in higher drain-to-source breakdown voltages (VBK) as the source-to-substrate path takes up part of the drain-to-source voltage (VDS) at the OFF state. In this work, we systematically investigate the impacts of substrate termination on dynamic performance of GaN-on-Si power devices. The devices used in this work are E-mode GaN MIS-FETs featuring a fully recessed gate and a SiNx gate dielectric. The OFF-state VBK is 1028-V with an FS termination and 727-V with a GS termination. Dynamic RON of the MIS-FET with different substrate terminations was characterized using a high-voltage high-speed pulsed I-V measurement system. The measurement configurations include pulse/period = 5/100 μs and quiescent drain bias up to VDSQ = 650 V. Compared to the GS termination, the FS termination induces more severe (by ~30%) dynamic RON degradation under medium VDSQ (< 300 V), when a transient negative substrate voltage is captured, revealing a charge storage process in the substrate. The smaller dynamic RON degradation at higher VDSQ (> 400 V) can be explained by the reduced vertical leakage from Si substrate to the drain and then alleviated electron trapping in the buffer. Thus, a floating substrate termination could simultaneously bring the benefits of high breakdown voltage and better dynamic RON and should be considered in the packaging design of GaN-on-Si lateral power devices.

Resume : GaN-based heterostructures are considered an excellent candidate for high-voltage (HV) power devices due to their superior material properties. However, GaN-based FETs suffer from RDSON shift that leads to high power loss and unreliable operation, in particular at high-voltage and high temperature conditions. RDSON shift is predominantly due to electron trapping across the Epi-layer(s), near the Epi layer/Si interface, and at/near the interface between dielectric layer and AlGaN top barrier near the gate. The main contributor attributed to RDSON shift in HV-GaN power devices is the buffer layers. However, we found that the electron trapping at/near the interface between the dielectric layer and AlGaN barrier near the drain contact is also a very critical contributor to the RDSON shift. GaN cap addition with Al fraction adjustment in AlGaN barrier increases the surface barrier height due to the enhanced polarization effect, reducing a possibility of electron trapping at the dielectric layer/GaN cap interface. A new proposed mechanism with increased barrier height will be discussed in detail. Trapping mechanisms, characterization methodology of active traps with trap energy levels, and electron trapping at SiNx/(Al)GaN interface and across the buffer layers are discussed as main RDSON shifting factors. Finally, impact of different epi-splits on RDSON shifting behavior will be briefly depicted with a progress of epi-quality improvement in terms of RDSON stability post long-term stress.

Resume : We report on the material and device characterization of heterostructure field effect transistors fabricated on 200 mm GaN-on-Si (111) epitaxial material. Buffer isolation and 2DEG transport properties are analyzed in conjunction with an investigation of the impact of the C doping technique on the dynamic properties of the fabricated devices. We employed a structure optimized for low bow (5 - 10 µm concave) with a total nominal thickness of 3.9 µm, consisting of AlN/AlGaN step-graded interlayers, a GaN buffer and an AlGaN/GaN heterostructure with an AlN spacer as active device element. To achieve highly insulating buffers, the 2 µm thick GaN buffer layer was doped in one case to approx. 2E19 cm-³ using hexene as an extrinsic C source, in the other case, merely the temperature and pressure were reduced during epitaxy to achieve a high carbon incorporation rate from the metalorganic precursors. In comparison to the reference layer w/o any intentional C doping, the bow is slightly increased for both C-doped samples to 9 – 17 µm (concave). Both doping methods lead to similar high-voltage properties in terms of vertical buffer leakage (0.1 A/cm² @ 700 V). The extrinsically C-doped structure yields significantly enhanced carrier mobility at all carrier concentrations. Also, pulsed characterization reveals considerably faster charging and discharging of the buffer, leading to much improved dynamic properties as will be shown on transistor level.

Resume : Efficient heat dissipation is key to achieving high-power performance in GaN-based HEMTs. Epitaxial growth on substrates with high thermal conductivity such as SiC is desirable for GaN-based HEMTs intended for high-power applications. Another approach to improving heat dissipation is transferring the HEMTs to a foreign substrate with high thermal conductivity. We have been developing a transfer technique using an h-BN epitaxial lift-off technique. This technique enables us to freely choose the materials used as the foreign substrate. In this study, we transferred HEMTs to various substrates, such as sapphire, Si, SiC, copper, and diamond, and investigated the influence of substrate thermal conductivity ranging from 40 to 2000 W/mK on the thermal resistance of the HEMTs. AlGaN/GaN heterostructures were grown on an h-BN release layer deposited on sapphire substrate. After fabrication of the HEMTs, we mechanically released the devices from the sapphire substrate and attached them to the other substrates using Au-Au thermocompression bonding. The results show that the thermal resistance of the HEMTs linearly decreases with decreasing thermal resistivity of the substrate (the inverse of thermal conductivity). From a linear extrapolation, the thermal resistance of HEMT at the thermal resistivity of 0 mK/W is about 4 mmK/W, meaning that the thermal resistance of the epitaxial layer cannot be ignored for HEMTs on high thermal conductivity material.

Resume : We report on growth and characterization of highly resistive buffer structures for AlGaN/GaN power HEMT. Both step-graded AlGaN transition layers with carbon-doped (GaN:C) buffers, as well as AlN/AlGaN superlattice (SL) buffers were employed. All samples were grown in a state-of-the-art high throughput Planetary Metal-Organic Chemical Vapor Deposition (MOCVD) reactor (AIXTRON™ G5+ C), utilizing in-situ Cl2 cleaning. Uniformities of total thickness and AlGaN barrier Al composition are well below 1% (sigma/mean) for all samples. Compared to GaN:C buffer architectures, SL buffers of equivalent thickness revealed higher breakdown voltages under both forward and reverse bias. A 100-fold SL structure with 4.5 µm total stack thickness exhibits breakdown voltages as high as 900 V in forward and 800 V in reverse bias at room temperature, providing reasonable safety margin for 650 V applications. Subsequently, E-mode power transistors were fabricated with gate width Wg = 36 mm, gate length Lg = 0.8 µm and gate-to-drain separation Lgd = 6 µm. A positive threshold voltage of +1.16 V was derived from a linear extraction of transistor transfer curves at maximum transconductance at Vds = 0.1 V. All devices exhibit low on-resistances of 5.7 Ohm-mm ± 0.19 Ohm-mm across the entire 200 mm wafer, demonstrating superior uniformities achievable with the Planetary MOCVD reactor design.

Resume : Vertical GaN based transistors are desired due to their reduced wafer “foot print”, in comparison to lateral HFETs that results in a reduction of RDS_ON × A by one order of magnitude down to ~1.0 mOhm∙cm2 and in reduced dispersion and switching losses. In addition, the possibility of strain free homoepitaxy allows the growth of thick drift layers for blocking capability larger than ~1 kV. Recent progress in the development of low defect density GaN substrates facilitates high voltage blocking. In this review, we compare several prominent concepts for vertical GaN transistors: Current Aperture Vertical Electron Transistors (CAVETs), Regrown Semipolar channel and p type gate structure, Trench gate MOSFET and newly Vertical FinFETs. Particular challenge of the first two concepts is the epitaxial regrowth and limited blocking capability. The MOSFET owns the advantage of one step epitaxial growth, normally OFF device nature and low gate leakage. On the other hand, it requires a robust gate insulating layer to allow a space charge region for channel inversion and for good transport properties. A vertical MOSFET grown by MOVPE on GaN substrate is demonstrated at FBH. When comparing the transistors characteristics after annealing it is observed that the ON resistance reduces from 12 kOhm∙mm to 150 Ohm∙mm, the ON OFF ratio increased from 10^6 to 10^8 and Ids_max increases from 0.25 mA/mm to 40 mA/mm, and blocking of 70 V/µm.

Resume : GaN is a promising material for high frequency and high power devices due to its wide band gap, high electron velocity, high breakdown field strength, and high thermal conductivity. Owing to the availability of free-standing GaN substrates from several vendors, vertical GaN devices on GaN substrates have progressed recently. Although the dislocation density of the GaN substrates is in the range of 1e4 to 1e6 cm-2, which is still considerably higher than those of Si and SiC substrates, vertical GaN devices on GaN substrates with excellent high-voltage and high-current characteristics have been reported. In this paper, recent progress of vertical GaN power devices fabricated on GaN substrates is presented with particular emphasis on the SBDs and the trench MOSFETs we developed. A vertical GaN SBD with simultaneous high forward current of over 50 A and high blocking voltage exceeding 800 V was fabricated, which exhibited excellent reverse recovery characteristics. Normally-off vertical GaN trench metal-oxide- semiconductor field-effect transistors (MOSFETs) with a blocking voltage of 1.6 kV were demonstrated by using a field-plate edge termination technique. In addition, by optimizing channel and drift layer structures and adopting regular hexagonal gate layout, a specific on-resistance was reduced to as low as 1.8 mohm•cm2 while maintaining a blocking voltage of 1.2 kV. By using these technologies, large chip trench MOSFETs were fabricated and over 10 A operation with fast switching characteristics was demonstrated.

Resume : We have investigated the IV-characteristics of GaN high electron mobility transistors (HEMTs) grown on 150 mm-diameter Si (111) substrates by metalorganic vapor phase epitaxy (MOVPE). High crystal quality GaN layers with a total thickness of 7 µm and without any crack, bow or meltback etching issues were successfully grown by an optimized combination of nucleation/buffer layers on the Si substrate and interlayers inserted into the GaN layers. Typical XRD FWHM (002) and (102) were 330 and 420 arcsec respectively and excellent XRD FWHM uniformity was realized with a standard deviation of 3 %. As a result of the high crystal quality GaN the vertical leakage current from top surface to bottom substrate was suppressed to 0.07 µA/mm2 at a reverse bias of 600 V. These results were achieved even without carbon doping into GaN which is often used to obtain high insulation of GaN layers but can cause issues on, for example, dynamic switching performance. Several industry standard MOVPE systems were used to grow the same proprietary ALLOS GaN-on-Si HEMT structure. Interestingly different optimization steps were required to grow the same HEMT structures in different MOVPE systems but once we obtained similar wafer-level properties such as XRD FWHMs, very comparable device properties were obtained irrelevant of the used MOVPE system. This indicates that the excellent performance from the high quality of GaN is independent of the MOVPE systems.

Resume : Owing to its high breakdown electric field and high electron saturation velocity, Gallium Nitride (GaN) is ideal for devices requiring high-power and high-speed operation. In order to realize a normally-off vertical GaN MOSFET for power conversion, the deposition of insulator films, which have high reliability and low interface state density (Dit), is required. However, not much is known about the Dit of GaN in each crystal plane. Therefore, it is necessary to understand the crystal plane dependence of Dit in GaN MOS structure. In this study, we investigated the Dit correlations of the c-plane, just m-plane, and off-cut angles of 5° with the [0001] (known as “c+5 degree”) m-plane GaN substrate. The MOS capacitors were fabricated on n-type GaN epitaxial layers, which were grown on n-type c-plane, just m-plane, and c+5° m-plane GaN substrates. The thickness of each epitaxial layer and the radius of each gate electrode were 4 and 250 microns, respectively. For the gate insulator, aluminum oxide (Al2O3) was deposited using Atomic Layer Deposition (ALD) at 350 °C. The thickness of Al2O3 was 20 nm due to the accumulation condition of the C-V characteristics. After the fabrication of the gate and back electrode, Dit was estimated using the Hi-Lo method at 300K. From the resulting C-V characteristics, it was observed that there was a decrease in the hysteresis, flat-band voltage shift, and frequency dispersion of the just m-plane and c+5° m-plane GaN MOS capacitors, when compared to those of the c-plane MOS capacitors. In addition, the Dit of the m-plane GaN MOS capacitors was found to be in the range 10^10–10^11 cm^-2eV^-1, using the Hi-Lo method. These results indicate that the Al2O3/m-plane GaN interface can improve the channel mobility of vertical GaN MOSFETs.

Resume : Several reports have analyzed leakage currents in Schottky barrier diodes using conductive atomic force microscopy. These concluded that leakage currents are caused by screw dislocations. However, only a few reports have attempted to identify the origin of leakage currents in vertical p–n diodes. Here we focus on the correlation between dislocation and leakage in a vertical p–n diode. We identify the killer dislocation by combining emission microscopy (EMS), cathode luminescence (CL), etch pits, and scanning transmission electron microscopy (STEM). A vertical p–n diode with a breakdown voltage of −600 V was prepared. When a voltage less than but near to the breakdown voltage was applied to it, dot-like leakage points were observed by EMS. The CL pattern of the same device revealed that part of each dark spot corresponds to leakage, which is clear evidence that dislocations cause leakage. The device was then etched in molten KOH, and three diameters of pit (large: 3 μm, medium: 1.5 μm, and small: 0.5 μm) were observed. Compared with the leakage site observed by EMS, only the medium-sized pits were found to cause leakage. STEM observations under these pits revealed that the large-sized pits are pure screw dislocations, whereas the medium- and small-sized pits are complexes of mixed and edge dislocations. These results are new evidence that pure screw dislocation is not responsible for leakage in p–n diodes. The presentation will discuss the details of the type of dislocation that forms medium-sized pits. This work was supported by Ministry of Education, Culture, Sports, Science and Technology of Japan, “the next-generation semiconductor R & D that will contribute to the realization of energy-saving society.”

Resume : It is well known that the introduction of field plate increases the breakdown voltage of AlGaN/GaN HEMTs [1, 2]. However, it increases the parasitic capacitance, leading to the degradation of high-frequency performance. As another way to improve the breakdown voltage, using a high-k passivation layer is proposed and analyzed [3]. But, it should have high interface-state densities, degrading the device performance. Therefore, in this study, we propose a structure with double passivation layers where the first passivation layer is a thin SIN layer having low interface-state densities and the second passivation layer is a high-k dielectric, and study how the breakdown voltage is enhanced. The analyzed device structure has the gate length LG of 0.3 μm and the gate-to-drain distance LGD of 1.5 μm. The thickness of first passivation layer (SiN) d1 is 0.01 μm and the relative permittivity is 7. The thickness of second passivation layer d2 and its relative permittivity εr2 are varied as parameters. In a buffer layer, we consider a deep donor and a deep acceptor [4, 5], and the deep-acceptor density NDA is set to 10^{17} cm^{-3}. We compare the calculated off-state drain current ID – drain voltage VD curves of AlGaN/GaN HEMTs as a parameter of d2 with a single passivation layer (SiN, εr2 = 7) and double passivation layers having a high-k dielectric (εr2 = 20). In the case with a single passivation layer of SiN, ID increases suddenly due to impact ionization, showing breakdown. In the case with double passivation layers, ID increases suddenly at thin d2. But when d2 becomes thick, ID increases gradually, reaching a critical value of ID (1 mA/mm) which corresponding to the breakdown. In this case, the buffer leakage current determines the breakdown voltage. The breakdown voltage Vbr versus the thickness of second passivation layer d2 curves clearly shows that Vbr becomes higher for the double passivation layers (εr2 = 20), particularly for thicker d2. This is because the electric field at the drain edge of the gate is reduced in the case of double passivation layers with a high-k dielectric. Vbr becomes nearly 300 V when d2 is 0.2 μm. We also calculate ID-VD curves of AlGaN/GaN HEMTs with double passivation layers as a parameter of relative permittivity of second passivation layer εr2, where d2 = 0.09 μm (d1 + d2 = 1 μm). When εr2 is low, the drain current increases suddenly due to impact ionization, as in a case of single passivation layer. But, as εr2 becomes high, the drain current increases gradually and reaches the current level of breakdown. The breakdown voltage Vbr increase as εr2 becomes high. Vbr can be nearly 300 V when εr2 is 30 even for thin d2. The value of Vbr = 300 V corresponds to an average electric field of 2 MV/cm between the gate and the drain. [1] S. Karmalkar and U. K. Mishra, IEEE Trans. Electron Devices, vol.48, p.1515 (2001). [2] E. Bahat-Treidel et al., IEEE Trans. Electron Devices, vol.57, pp.1208 (2010) [3] H. Hanawa, H. Onodera, A. Nakajima and K. Horio, IEEE Trans. Electron Devices vol.61, p.769 (2014). [4] K. Horio, K. Yonemoto, H. Takayanagi, and H. Nakano, J. Appl. Phys., vol.98, 124502 (2005). [5] K. Horio, H. Onodera, and A. Nakajima, J. Appl. Phys., vol.109, 114508 (2011).

Resume : AlGaN/GaN HEMTs are now receiving great interest for application to high-power microwave devices and high-power switching devices [1, 2]. To improve the breakdown voltage, the introduction of field plate is shown to be effective [3], but it may increase the parasitic capacitance, leading to degrading the high-frequency performance. In a previous work [4], as another method to improve the breakdown voltage, we proposed a structure including a high-k passivation layer, and showed that the breakdown voltage increased significantly. We assumed an undoped semi-insulating buffer layer where a deep donor compensates a shallow donor. Recently, Fe- and Cr-doped semi-insulating buffer layers are often adopted and they acts as deep acceptors [5, 6]. Therefore, in this work, we analyze AlGaN/GaN HEMTs with a buffer layer including only a deep acceptor, and studied how the breakdown voltage is influenced. The device structure analyzed here has the gate length LG of 0.3 μm and the gate-to-drain distance LGD of 1.5 μm. The thickness of SiN layer d is 0.1 μm. As a buffer layer, we consider a Fe-doped semi-insulating layer, and the Fe level (EDA) is typically set to 0.5 eV below the bottom of conduction band (EC) [5], and its density NDA is set to 10^{17} cm^{-3}. We calculate drain current ID – drain voltage VD curves and gate current IG – drain voltage VD curves as a parameter of the relative permittivity of passivation layer εr. The gate voltage VG = – 8 V, which corresponds to an off state. When εr is low (< 20), a sudden increase in drain current due to impact ionization determines the breakdown voltage Vbr. When εr becomes high (≥ 30), ID reach a critical value (1 mA/mm) before a sudden increase in ID, and in this case the buffer leakage current determines Vbr. Vbr is defined here as the drain voltage when ID becomes 1 mA/mm. Vbr increases as εr increases. This is because the electric field at the drain edge of the gate is reduced when εr becomes high. We compare Vbr versus εr curves between the two cases with different buffer layers. In the undoped semi-insulating buffer layer, the deep donor’s energy level (EDD) is set equal to EDA in the Fe-doped semi-insulating buffer layer. The deep-acceptor densities NDA are both set to 10^{17} cm^{-3}. Vbr is nearly equal when εr is low, but becomes a little higher in the case of Fe-doped buffer layer when εr is high. This is because the Fermi level in the bulk of buffer layer is a little further from the conduction band, and hence the buffer leakage current becomes lower. Next we calculate ID-VD curves when EDA is 0.56 eV below EC, a little deeper than that before. The sudden increase in ID when εr is low is similar to that mentioned before, but when εr is high (≥ 30), the drain currents becomes rather low. We compare Vbr versus εr curves with different EDA. When EDA is deeper, Vbr in high εr region is rather higher. This is because the buffer leakage current becomes lower due to the higher electron barrier at the channel-buffer interface. [1] U. K. Mishra, L. Shen, T. E. Kazior, and Y.-F. Wu, Proc. IEEE, vol.96, p. 287 (2008). [2] N. Ikeda, Y. Niiyama, H. Kambayashi et al., Proc. IEEE vol.98 p.1151 (2010). [3] S. Karmalkar and U. K. Mishra, IEEE Trans. Electron Devices, vol.48, p.1515 (2001). [4] H. Hanawa, H. Onodera, A. Nakajima and K. Horio, IEEE Trans. Electron Devices vol.61, p.769 (2014). [5] M. Silvestri, M. J. Uren, and M. Kuball, Appl. Phys. Lett. vol.102, 073051 (2013). [6] J. Hu, S. Stoffels, S. Lenci et al., IEEE Electron Device Lett. vol.37, p.310 (2016).

Resume : We have studied majority carrier traps in AlGaN/GaN HEMTs by drain current DLTS using gate bias pulses. Moreover, minority carrier traps are observed by MCTS using above-band-gap light pulses. It is important to make a direct characterization of traps in HEMTs, instead of using Schottky diodes, to understand current collapse of devices used. Traps observed in HEMTs are compared with those in n-GaN Schottky diodes. Devices used are Al0.25Ga0.75N/GaN HEMTs fabricated by MOCVD on Si substrates. DLTS spectra are obtained by measuring drain current transients with the capture gate bias of 0 V and the subsequent emission gate bias of – 3 V near the threshold voltage Vth. MCTS spectra are obtained using the ~355 nm LED as an optical source of the above-band-gap light with the gate bias of -3 V. For the purpose of comparison, Schottky diodes are fabricated on MOCVD n-GaN on Si. Three traps are observed as positive peaks in HEMTs by temperature-scan DLTS in the temperature range from 80 to 370 K. The energy levels are obtained by Arrhenius plots of emission time constants which are determined from isothermal DLTS spectra since temperature-dependent mobility and threshold voltage might distort temperature-scan DLTS spectra. The energy levels are estimated to be Ec-0.24, Ec-0.44 and Ec-0.81eV for observed three traps. In n-GaN Schottky diodes, three electron traps are also observed by DLTS whose energy levels are consistent with those of traps observed in HEMT, respectively. It is found that three traps in HEMTs are the same electron traps in n-GaN Schottky diodes. The filling behavior of electron traps observed in HEMTs are studied using isothermal DLTS in the filling pulse width range from 1E-1 to 1E+4 s. All three traps show the logarithmic filling behavior, indicating that these traps are associated with dislocation-related defects. The trap concentration is obtained using the saturated value of ΔVth in the filling behavior which is calculated from the drain current DLTS peak height, assuming that the observed region by DLTS is under the gate. The areal trap concentrations with the energy levels of Ec-0.24, Ec-0.44 and Ec-0.81 eV are estimated to be 5.0E+10, 3.0E+11 and 3.2E+11 cm-2, respectively. Temperature-scan MCTS spectra in HEMT reveal two negative peaks, indicating the presence of two hole traps. Two hole traps are also observed in MCTS spectra for n-GaN Schottky diodes. Their energy levels are consistent with each other between HEMTs and n-GaN Schottky diodes and are found to be Ev+0.25 and Ev+0.86 eV. The areal trap concentrations with the energy levels of Ev+0.25 and Ev+0.86 eV in HEMT are estimated to be 2.2E+11 and 4.8E+11 cm-2, respectively. In summary, we have observed three electron traps and two hole traps in AlGaN/GaN HEMTs on Si using drain current DLTS and MCTS. Their energy levels and areal trap concentrations are reported. These traps observed in HEMTs are all detected in n-GaN Schottky diodes on Si. These results seem to suggest that the undoped GaN channel layer under the AlGaN barrier layer is slightly n-type, although further study is needed to obtain the decisive conclusion. This work has been performed as an MEXT-Supported Program for the Strategic Research Foundation at Private Universities (2010-2014).

Resume : Vertical GaN diodes have recently been improving their performances in on-resistances (Ron) and breakdown voltages (VB) for efficient power applications. It is well known that a hole concentration in a Mg-doped p-GaN layer reaches maximum at Mg concentration of 2e19 cm-3, above which the hole concentration decreases by formation of crystalline defects. Here we report that very thin (10-20 nm) and highly Mg-doped p+GaN (Mg=2e20 cm-3) layers have been suitable for hole injector as well as lowering ohmic contact resistances. The mesa-structure p-n junction diodes were fabricated with p+GaN(Mg=2e20 cm-3)/n-GaN(Si= 1e16 cm-3, 5000 nm) epitaxial layers grown by MOVPE on free-standing GaN substrates. The thicknesses of the p+GaN were 10, 20, and 400 nm. At the thickness of 400 nm, the epitaxial layer showed rough surface morphology, very low hole concentration (<1e16 cm-3) and dark photoluminescence by defect formation. On the other hand, at the thickness of 10-20 nm, the smooth surface was maintained and high performance p-n junction diodes were fabricated with very low Ron (0.5 mohmcm2) at 4 V. Turn-on voltage was 3.0 V above which strong electroluminescence was observed. VB was more than 900 V. These results suggest that the p+GaN layer can be used for the GaN diodes as far as its thickness is limited within a few decades nm. These findings can make the diode efficient because we can omit the typically used thick Mg-doped (1e19 cm-3) p-GaN layer which increases Ron.

Resume : Aluminum gallium nitride/Gallium nitrides high electron mobility transistors are excellent candidates for next generation commercial wireless base station amplifications, high-voltages, high-power and high-temperature. These heterostructures contain spontaneous and piezoelectric polarization fields leading to the formation of an interfacial two-dimensional electron gas. These remarkable performances can be obtained by optimizing accurately the device fabrication and material growth. Particularly, with regard to device manufacture, development of high quality surface passivations significantly reduces the surface trap induced of current collapse which is a critical problem in AlGaN/GaN HEMTs and decreases the density of traps at the surfaces.

Resume : Wide band-gap and high breakdown electric field allows high terminal voltage operation of the transistor based on Gallium nitride technology. The excellent microwave power performance demonstrated in AlGaN/GaN HEMTs (high-electron mobility transistors) results from the combination of high current density with high voltage operation [1], which benefits from the high sheet charge density in these hetero-structures (1013 cm-2), the high carrier mobility (1500 cm2/Vs) and saturation velocity (1.5 × 107 cm/s) in the channel and the high breakdown voltage inherent in the GaN material. However, their reliability still limits their applications in today’s electronic systems. The newly developed Gate Field-Plated AlGaN/GaN high electron mobility transistors show improved performance due to the electric field reduction in the device channel and surface modification [2]. We report on two dimensional numerical simulations of Gate-Recessed and Field-Plated AlGaN/GaN HEMTs where all the important device parameters have been defined, the insulator thickness and permittivity under the Gate Field-Plated is also an important design parameter to attain higher breakdown voltage, thus an improvement of the performances of HEMTs. 1. Y. F. Wu, A. Saxler, M. Moore, R. P. Smith, S. Sheppard, P. M. Chavarkar, T. Wisleder, U. K. Mishra, and P. Parikh, IEEE Elect. Dev. Let., 25, 117 (2004) 2. K. H. Cho, Y. S. Kim, J. Lim, Y. H. Choi, M. K. Ha, Sol.Stat. Elect., 54, 405 (2010).

Resume : Ti0.5Al0.5O-dielectric Al0.26Ga0.74N/GaN metal-oxide-semiconductor high electron mobility transistors (MOS-HEMTs) grown on a Si substrate are investigated. The Ti0.5Al0.5O gate dielectric was grwon by using a cost-effective non-vacuum ultrasonic spray pyrolysis deposition (USPD) technique. The effective oxide thickness (EOT) was determined to be 2.68 nm with high dielectric constant k = 9.01. Improved interfacial quality is studied by comparisons of Hooge coefficient (αH), low-frequency noise spectra (1/f), pulse I-V characteristics. As compared to a reference Schottky-gate HEMT, superior improvements have been achieved for the present MOS-HEMT design, including 23% in maximum drain-source current density (IDS, max), 31% in gate-voltage swing (GVS) linearity, 3-order increases in on/off current ratio (Ion/Ioff), 46.3% in two-terminal off-state gate-drain breakdown voltage (BVGD), 65% in three-terminal drain-source breakdown voltage (BVDS), 28% in unity-gain cut-off frequency (fT), and 46% in maximum oscillation frequency (fmax). Enhanced power performances and thermal stability at 300-450 K are also obtained. The present design is advantageous to high-gain and high-power circuit applications.

Resume : AlGaN/GaN HEMT sensor is an attractive alternative to Si-based one because GaN-based materials have excellent chemical stability and high temperature endurance. In this paper we report the development results of AlGaN/GaN HEMT based sensor platform and its H2 sensing results with HEMT design variations. The heterostructure was grown on a 4-inch sapphire substrate by metalorganic chemical vapor deposition, which consists of a 3-um-thick GaN layer and a 21-nm-thick Al0.25GaN layer. The sheet carrier concentration of 1.0E 13 /cm^2 and the mobility of 1800 cm^2/V-s were obtained. Isolation was achieved by ICP plasma. An ohmic metal of Ti/Al/Ni/Au was deposited and annealed. An pad metal was formed for probing. The devices were passivated with SiNx. The dielectric film on the gate regions was wet-etched and proper detection materials were deposited on it. To test the sensor platform, we fabricated the hydrogen sensor using Pt as detection material and compared the sensitivity with gate length variation of 2, 6, and 10 um, respectively. I-V characteristics were measured before and after exposing to 4 % H2 in N2 at room temperature. The drain bias was fixed at 1 V and the gate bias was varied from – 4 to 2 V. The device with the gate length of 6 um exhibited the relative current change of 1.1E 6 % at the gate bias of -3.1V, which is the maximum value among those. We will present the sensing properties dependency of HEMT design and measurement condition variations in conference.

Resume : The typical current-voltage relationship predicted by basic thermionic emission modeling, namely, J = A*T^2 exp (-qVb /kT) [exp (qV/kT)-1], (qVb the junction barrier, V the applied voltage, and A* Richardson’s constant) does not include specific carrier transport mechanisms that occur across the graphene/semiconductor Schottky junction (G/n-Si junction). In a reverse biased G/Ox/n-Semiconductor junctions, graphene’s Fermi level shifts upwards relative to the semiconductor’s quasi-Fermi level, through the reversely applied voltage though the junction. Reverse current (G to Si side) is feasible via thermionic escape and subsequent tunneling. In this communication we propose a way of re-writing, from first principles, the formula for thermionic field-emission carrier transport across a non-ideal Schottky G/Oxide/n-Si junction under reverse bias. We explore field emission in Graphene/Oxide/n-Semiconductor (G/Ox/n-S) Schottky junctions under reverse bias. We consider graphene replacing the metal region of a Schottky diode and study field emission through a double barrier composed of the oxide layer and the semiconductor contact layer. Specifically, we model Dirac fermions thermionically escaping from graphene and reaching the semiconductor side (under reverse bias) by tunneling through the double barrier region. Two explicit transmission coefficients are included, namely, transmission through the oxide T(ox) and transmission through the semiconductor contact potential T(s). We model tunneling through these barriers separately and include them in a generalized Landauer formula for direct tunneling current calculation. We model carrier escape in a Landauer formalism, by expressing the current over or through the Schottky junction spike, namely, , where q is the electronic charge, tg is the thickness of the graphene layer D(E) is graphene’s linear DOS (density of states), fg,S are the Fermi-Dirac carrier probability functions, v(E) is the thermal electron velocity, and t(E) is the transmission probability over (=1) and through (less than 1) the barrier. Starting from the last integral, we model migrating carriers through two transport mechanisms (a) thermionic escape (TE) over the junction barrier and (b) thermionic field emission (TFE) through the barrier.

Resume : Normally-off (or E-mode) AlGaN/GaN heterostructure field-effect transistors (HFETs) are promising candidates for power switching devices and RF and microwave circuits because of its inherent fail-safe property and simple gate control circuitry. Up to now, various approaches have been proposed for E-mode HFETs fabrication, among which the trench gate scheme with a fully recessed and insulated gate may be the most promising technique owing to high threshold voltage (Vth) and gate voltage swing. However, the surface damage during recess process as well as the scattering of insulator/GaN interface will cause a lower channel mobility. Partially recessed barrier layer is help to avoid mobility degradation, but at the cost of relatively smaller Vth, smaller gate forward turn-on voltage, and larger forward gate leakage current. p-GaN gate formed on AlGaN barrier layer can lift up the potential at the channel and realize normally-off device with high channel mobility. However, it is very difficult to epitaxy p-GaN on a recessed gate area with high quality and good uniformity. On another hand, NiO behaves as a natural p-type semiconductor and shows excellent chemical stability. It can be fabricated using reactive sputtering or thermal oxidation at room temperature or relatively lower temperature. Those make NiO a promising gate material to adjust band structure and then achieve normally-off AlGaN/GaN HFETs. Herein, p-type NiO films were formed though oxidizing 30 nm Ni metal (deposited on double-sides polished sapphire substrates by electron-beam evaporation) in oxygen ambient (0.3 SLPM) at 400, 500, 600, and 700 ?, respectively, for 10 min. AFM results show that all samples oxidized at different temperatures present similar rough surface with the roundish particle diameter fluctuating at different areas (RMS is approximately 5 nm at 3?m×3?m scaled). Room-temperature Hall measurement shows all NiO thin films exhibit p-type semiconducting behavior. The resistivity first increased significantly from approximately 4.8 k?/sqr to 30 M?/sqr with increasing temperature from 400 to 500 ?, then it increased slightly to approximately 90 M?/sqr at higher oxidizing temperatures. However, the estimated values of hole concentrations are approximately 3.8×1017 cm?3 for sample obtained at 400 ?, which is nearly half of that of sample at higher oxidizing temperature (approximately 8.0×1017 cm?3). This abnormal electrical properties of samples oxidized at 400 ? was ascribed to the residual of Ni metal content in the film, because Ni metal was not be oxidized sufficiently at relatively low temperature. The electron in residual Ni will partially compensate the hole concentration, which provide better conductivity but worse optical transparency. This result can also be confirmed from the XRD, XPS and transmission spectrum. Based on the above findings, we chose NiO obtained at 500 ? as the optimum gate material for normally-off HFETs application. Normally-off devices were fabrication on AlGaN/GaN HFETs. After MESA isolation, the gate area was partially recessed with an etch depth of approximately 10 nm using Cl2/BCl3-based dry etching. Then, ohmic contact metal consisting of Ti/Al/Ni/Au (15/80/25/60 nm) is deposited with electron-beam evaporation and annealed at 870 ? for 30 s in nitrogen ambient. After Ni metal (30 nm) is deposited, one of samples was post oxidize at 500?. The transfer and transconductance characteristics of the HFETs with Ni and NiO gate electrodes were measured at Vd=8 V. The non-recessed Ni-gated HFETs showed a threshold voltage of approximately -3 V, while it shift to approximately -2 V for the NiO-gated HFETs. The transconductance of the NiO-gated HFETs shows slight degradation compared with the Ni-gated one. Gate recess process is a powerful method to obtain normally-off devices. After recessed for 10 nm (residual AlGaN thickness is approximately 14 nm), threshold voltage of both the Ni- and NiO-gated HFETs positively shift approximately 2 V. Finally, combining the gate recess and p-type NiO material, normally-off HFETs can be obtained with high transconductance.

Resume : Vertical GaN power devices have recently been drawing attention because of their potential on high power conversion efficiency. Here we report that electroluminescence (EL) intensity mappings under forward biased conditions on the p-n junction plane beneath circular anode electrode have revealed microscopic non-uniformities in several featured GaN p-n junction diodes. The mesa-structure p-n junction diodes were fabricated with p+-GaN/p-GaN/n-GaN epitaxial layers grown by MOVPE on free-standing GaN substrates. EL-intensity mappings were observed through ITO transparent electrode on the back side of the diodes. The epitaxial wafer had deviation in chacteristic surface roughness caused by c-axsis distributions within the GaN substrate with a diameter of 2 inches. Featureless smooth area coexisted with wavy surface area on the wafer. The diode fabricated on the smooth area showed EL distribution with high intensity ring with a width of 10 microns at the edge of the electrode and uniform intensity at inner area. This EL distribution proved Mochizuki's prediction for photon-assisted conductivity modulation in p-GaN layers. On the other hand, striped EL mapping images were obtained with diodes having wavy surface with complete correspondence with the morphologies. TOF-SIMS mapping clarified that Mg density in the p-GaN distributed as the morphology. Forward on-resistances of the diodes with the smooth surfaces showed lower values than those with the wavy morphologies.

Resume : GaN high electron mobility transistors (HEMTs) on silicon substrates are promising for future efficient and low-cost power conversion. The tri-gate architecture has recently attracted large attention for GaN HEMTs, offering excellent gate control that results in reduced leakage current, as well as new prospects for normally-off operation. However, to form the tri-gate region, a portion of the 2-dimensional electron gas (2DEG) is removed during the nanowire etching, which causes large degradation in on-resistance and output current. In addition, the potential of GaN tri-gate HEMTs for power applications have not been yet presented, as current tri-gate HEMTs and other nanowire-based devices exhibit limited breakdown voltage. In this work, we present high-performance tri-gate GaN power MOSHEMTs on silicon substrates exhibiting no degradation in ON-state performance, as well as state-of-the-art voltage-blocking capability in OFF-state. The fabricated tri-gate transistors were similar to conventional planar GaN transistors, except that part of the gate region was patterned with periodically spaced nanowires covered by a 20 nm-thick Al2O3 layer and Ni/Au gate metal to form the tri-gate region. The length and width of the nanowires were 700 nm and 600 nm, respectively, spaced by 150 nm-wide etched trenches, which corresponded to a large filling factor of 80%. For a fair comparison, the device characteristics such as on-resistance, drain current, leakage current as well as transconductance were normalized by the width of the entire device (60 μm) in both planar and tri-gate devices, and their error bars were determined from measurements on up to 10 separate devices of the same kind. The tri-gate MOSHEMTs (Tri-gate) presented larger on/off-current ratio with a similar drain current and on-resistance as compared to the planar MOSHEMTs (Planar), indicating no ON-state degradation despite the partial removal of carriers by nanowire etching. This is mainly due to the optimized tri-gate geometry including: 1. large filling factor, which increased the effective channel width; 2. reduced length of nanowires, which reduced the area of etched regions; 3. narrow etched trenches, which led to small spreading resistance and offered additional conduction channels operating as MOSFETs in parallel with the nanowire MOSHEMTs. In OFF-state, the Tri-gate exhibited smaller leakage current and much higher breakdown voltages as compared to the Planar. With a gate-to-drain separation of 5 μm, the Tri-gate presented a high breakdown voltage of 792 V at 0.3 μA/mm along with a small on-resistance of 0.91 ± 0.08 mΩ·cm2, despite the removal of 2DEG in the tri-gate region. This yielded an improvement of ~500 V in breakdown with respect to the Planar and, to the best of our knowledge, the smallest on-resistance among GaN-on-silicon (MOS)HEMTs with breakdown voltage larger than 700 V. With a gate-to-drain separation of 15 μm, the Tri-gate exhibited a breakdown voltage of 1370 V at 1 μA/mm, very close the best reported value for GaN-on-silicon transistors (with 7.3 μm of carbon doped buffer layers), despite its much thinner buffer of 3.75 μm. These results reveal the outstanding potential of nanowire approaches for high-voltage and low-leakage GaN power devices.

Resume : I. Introduction Own to their high speed and low off-state leakage, GaN based enhancement-mode transistors are a major attraction for Enhancement/Depletion-mode (E/D-mode) logic circuits for digital and mixed-signal applications. There have been several techniques used to fabricate E-mode devices to date, all incorporating different technologies to empty the two dimensional electron gas (2DEG) channel underneath the device gate (at zero gate bias) necessary for a normally-off operation. In order to achieve this, E-mode GaN transistor have been developed with various techniques, including gate recess, dual-gate integration, tri-gate structure, fluorine plasma treatment, PN junction Gate structure, N-Polar GaN HEMTs, among others. However, it is difficult to use these methods to fabricate devices that simultaneously high breakdown voltage, low off-state leakage and high drain current density. For E-mode recess gate AlGaN/GaN HEMTs acting as a popular structure, the gate leakage current is the main contributor to off-state leakage current due to employment of recess Schottky gate. For E-mode dual-gate integration or tri-gate structure AlGaN/GaN devices, the field plate (FP) structures increase gate-drain capacitance and reduce gain. For E-mode PN junction gate devices, the impurity scattering makes the carrier mobility degradation obviously and reduce saturation current. For E-mode N-polar AlGaN/GaN HEMTs, the devices show the threshold voltage roll-off under the high drain voltage. Thus, high breakdown voltage, low off-state leakage and high drain current density for E-mode AlGaN/GaN HEMTs deserves to be studied. In this letter, we applied recessed trapezoidal groove dual-gate architectures to AlGaN/GaN E-mode transistor design, increasing the lateral broadening of depletion region and depleting the 2DEG channel underneath the recessed trapezoidal groove dual-gate, to minimize the gate leakage and off-state leakage. The low-damage gate recess allowed for fabrication of high quality Schottky contact. A direct current performance with a maximum drain current density of 480mA/mm, an extrinsic trans-conductance of 308mS/mm, and off-state leakage current of ~10-10A/mm was demonstrated. Gate induced drain leakage effects have been greatly improved with recessed trapezoidal groove dual-gate structure. A ft of 32GHz and an fmax of 65GHz achieved by the recessed trapezoidal groove dual-gate architecture. It is also believed to firstly report AlGaN/GaN E-mode Transistor by using recessed trapezoidal groove dual-gate depletion enhancement effect. The details of the device structure, processing, dc and small signal performance will be explained in the following sections. II. Material Growth and Device Fabrication Process The un-doped AlGaN/GaN hetero-structure layers were grown at Xidian University on a 3-in semi-insulating 4H-SiC substrate by metal organic chemical vapor deposition. The epitaxial layers contain a 120-nm AlN nucleation layer, 1.2µm unintentionally doped GaN buffer, and 22nm Al0.25Ga0.75N barrier. Hall measurements show a carrier density of 0.8×1013cm-2 and an electron mobility of 2200 cm2/V•s. The sheet resistance is approximately 350Ω/□ at room temperature. The gate length of the RF gate (Vg1) was 130nm and the gate length of the DC gate (Vg2) was 250nm. Device processing started with Ti/Al/Ni/Au source and drain electrodes. These were annealed at 830℃ for 30s in a rapid thermal anneal. A transmission line method measurement showed ohmic contact resistance of 0.4Ω•mm. Device isolation was achieved by reactive ion etching using Cl2 plasma. 120nm SiN passivation was achieved with plasma-enhanced chemical vapor deposition. After definition of the gate recess regions, the over-etching SiN by low power CF4-based plasma can form trapezoidal groove profiles (the result of ion-scattering by the etch-stop layer). Then, the exposed AlGaN layer in the gate window formed by Cl2-based etching. The RMS of the recess area is 0.61 nm, and the smooth surface is a result of a low damage Cl2-based etching. The measured depth of the trench profile was 12nm. The Ni/Au gate metallization was done by liftoff processing. The gate overhang above the field plate SiN layer was 530nm for 130nm RF gate, and was 650nm for 250nm DC gate. The distance between the Vg1 and Vg2 was 0.3µm. All devices in this letter have a gate width of 2×50µm, a gate-source spacing of 1.2µm, and source-drain spacing (LSD) of 3.5µm. III. Device Performance and Discussion The threshold voltage (Vth) of recessed trapezoidal groove dual-gate device is 0.43V. A clear shift of Vth is observed as a result of recessed trapezoidal groove dual-gate design. By the atlas simulation of depletion region distribution in the recessed trapezoidal groove dual-gate device, we find the recessed trapezoidal groove structure helps increase lateral broadening of depletion region and then realizes fully depletion of 2DEG under the region where is between recessed trapezoidal groove Vg1 and Vg2. As a result of this depletion region enhancement effect, the recessed trapezoidal groove dual-gate design can achieve the enhancement-mode in the thicker barrier layer than the recessed steep groove dual-gate device. The saturation current and trans-conductance of the recessed trapezoidal groove dual-gate devices were 480mA/mm and 308mS/mm, respectively. . The trapezoidal groove dual-gate device shows excellent off-state leakage (~10-10A/mm), in comparison to recessed steep groove dual-gate devices. Meanwhile, the gate induced drain leakage effects have been improved effectively by the recessed trapezoidal groove dual-gate architecture design. These experimental results indicate that the extension enhancement of depletion region in the recessed trapezoidal groove dual-gate design can be effective in realizing the fully depletion of 2DEG and reducing off-state leakage.. A maximum 125V three-terminal breakdown voltage is achieved on a recessed trapezoidal groove dual-gate E-mode device at Vg1=-1.5V. A strong correlation between the Ioff and the Ig is observed. The lower the Ig, the lower the Ioff is. The Vg1 leakage maintains a low level even at Vd=100V. However, there is a rapid increase in the gate leakage of the recessed steep groove dual-gate device. The improvement of the gate leakage using the recessed trapezoidal groove dual-gate architecture is, thus, contribution to the suppression of the off-state leakage. At the same time, the Vg2 can cause an increase in the insolation between the Vg1 and the drain. The electrical potential difference nearby the Vg1 is effectively reduced. Therefore, the Vg1 leakage of the recess DG device further decreased and the breakdown voltage further improved. Due to high electrical potential between the Vg2 and drain, the leakage of Vg2 is higher than Vg1. S-parameters are measured in the frequency range from 0.1GHz to 40GHz. From S-parameter measurements, the fT and the fMAX of the recessed trapezoidal groove dual-gate device are determined by biasing the devices at Vg1=1.5V, Vg2=0V and Vd=5V. Under these conditions, it shows fT=32GHz and fMAX=65GHz. These values are obtained by extrapolating the short circuit current gain (H21) and the unilateral power gain (U) curves, respectively, using -20dB/dec slopesIn this letter, the recessed trapezoidal groove dual-gate E-mode GaN transistor has been designed, fabricated, and measured. IV. Conclusion We found that the recessed trapezoidal groove gate profile can increase lateral broadening of depletion region and finally make the extension enhancement of depletion region, yielding the E-mode operation. This type of E-mode device exhibits a threshold voltage of 0.43V, a maximum drain current of 480mA/mm, a trans-conductance of 308mS/mm, an off-state leakage current of ~10-10A/mm, a breakdown voltage of 125V, a fT of 32GHz, and an fMAX of 65GHz. An attractive feature of the recessed trapezoidal groove dual-gate E-mode device is the capability to decrease the gate leakage, off-state leakage, and improve the breakdown voltage. Such low off-state leakage, high breakdown voltage and high frequency enable the recessed trapezoidal groove dual-gate AlGaN/GaN E-mode HEMT very promising for high voltage drive circuit, low power and high speed circuit applications.

Resume : Ion implantation technique for controlling p-type conduction has been significant challenge for GaN-based electronic devices. In our previous report [1], the diodes fabricated by Mg/H coimplantation to a GaN(000-1) substrate exhibited distinct rectification at a turn-on voltage of about 3 V after annealing without protective layer. In this study, the Mg-related emissions from the Mg-implanted GaN(000-1) were investigated using low temperature cathode luminescence (CL). Mg with or without H ions were implanted to n-type GaN(000-1) and (0001) substrates at room temperature, and subsequently annealed at 1230°C for 30s in N2 gas. The maximum concentrations of Mg/H ions were 1.4×10^19 / 2.1×10^20 cm-3. This condition formed the 100-nm-thick p-type layers [1]. CL measurements were carried out at 10 K. For the ion-implanted GaN(000-1) samples, CL emissions at 3.457 and 3.272 eV were assigned to acceptor bound excitons (A0X) and donor-acceptor pairs (DAP), respectively, because their peaks corresponded to those of the p+/n diode grown by metal-organic vapor phase epitaxy. For the ion-implanted GaN(0001) sample, no A0X peaks was observed. Coimplantation with H ions enhanced DAP and suppressed the defect-related emission at 2.36 eV. These results clearly indicated that the defect-reduced-p-type GaN was achieved by the Mg/H-coimplantation for GaN(000-1). [1] T. Narita et al., Appl. Phys. Express 10, 016501 (2017).

Resume : AlGaN/GaN high electron mobility transistors (HEMTs) are one of the most promising candidates for high-power and high-frequency microelectronic devices. For power applications, a Schottky gate contact with large barrier height and low gate leakage current is always desirable to achieve high transconductance, maximum drain current, high turn-on voltages, high breakdown voltage of the device and low electronic noise. In this work, a higher barrier height and lower reverse bias leakage current was achieved by sandwiching a Self-Assembled Monolayer (SAM) of organic molecules between the most commonly used Ni gate electrode and AlGaN/GaN epitaxial films. SAM of Thiolated Porphyrin (TTPSH) organic molecules was adsorbed on the semiconductor side of the metal-semiconductor interface. The chemisorption of TTPSH SAM on AlGaN/GaN surface was confirmed by using Water contact angle measurements, X-ray Photoelectron Spectroscopy (XPS) and Atomic Force Microscopy (AFM). Kelvin Probe Force Microscopy (KPFM) revealed that the surface potential of the AlGaN/GaN sample was reduced from 1000 mV to 700 mV after the adsorption of SAM. A decrease in the surface potential of semiconductor side of the metal-semiconductor interface implies decrease in work function of the semiconductor which may lead to an increase in Schottky barrier height. Ni metal was deposited on the molecularly modified AlGaN/GaN surface and was electrically characterized by current-voltage (I-V) measurements. A significant increase in Schottky barrier height from 1.17 eV to 1.36 eV and a decrease in reverse bias leakage current by three orders of magnitude was obtained. Decrease in reverse bias current may be attributed to the presence of aromatic rings in porphyrin which hinders the metal diffusion through the SAM layer, thereby making the gate electrode more superficial.

Resume : GaN-based heterojunction bipolar transistors (HBTs) have inherent advantages, such as more uniform threshold voltages, higher linearity, normally off operation, and higher current densities compared with HEMT. However, the development progress on the GaN-based npn HBTs is slow. The major issue is the low conductivity in the base layer caused by the difficulty of achieving high free-hole concentration and the plasma-induced dry-etching damage on the extrinsic base region [1,2]. In order to relieve the damage of the base layer, many scholars are committed to improving the etching method [3,4]. Beside these, selective area regrowth(SAG) of base contact layer or emitter layer is also reported [5,6]. Although the utility of the selective area regrowth has advantage to improve the performance of HBTs, there is no significant progress after their work. One of the most common factors is that obtainment of high crystal quality selective area regrown base layer and emitter layer is difficult. This essay reports a AlGaN/GaN heterojunction bipolar transistor (HBT) on sapphire with regrown n-AlGaN emitter by using selective area growth method by metal-organic chemical vapor deposition (MOCVD). The fabricated HBT exhibits d. c. current gain (β) =7, and Jc=2.34KA/cm2 at VCE=13V. A 100 nm p-GaN / 0.5μm u-GaN/1μm n -GaN epitaxial wafer is grown by MOCVD on 2-inch c-plane sapphire substrates. Hall measurements performed on p-GaN base layer indicated a hole concentration of 9.8×1017 /cm3 and mobility of 14.1 cm2/V.s. A 100 nm-thick SiO2 mask layer are deposited on the wafer and patterned for select-area growth emitter. Then the wafer is reloaded reactor and a 100 nm-thick n-AlGaN emitter layer is grown under the temperature of 980 ℃. The Al composition of the AlGaN layer is determined by high-resolution x-ray diffraction (HR-XRD). Surface morphology of the regrown n-AlGaN layer is revealed by AFM. After removing the SiO2 mask by BOE, the base-collector (BC) mesa is etched by inductively coupled plasma (ICP) system, and a Ni/Ag/Pt metal stack is deposited and annealed as base ohmic contact. Then a Ti/Al/Ti/Au metal stack is deposited as emitter and collector Ohmic contact without annealed. Transfer length measurement (TLM) is used to measure the specific contact resistivity of the ohmic contacts. According to the HR-XRD result, the Al component is about 7.9%. The thickness of the regrown n-AlGaN is about 70 nm measured by scanning electron microscope (SEM). An atomically flat terraces-and-step structure can be observed distinctly. The value of the RMS is 0.215nm with the scan area is 2×2 μm2, reveal that the regrown n-AlGaN has a high crystal quality. Ohmic contacts are obtained on both the p-GaN base layer and the regrown n-AlGaN emitter layer. The sheet resistance (Rs) of the regrown n-AlGaN emitter layer determined by TLMs is approximately 934.6 Ω/sq, and the specific contact resistance (ρc) is 1.65×10-5 Ω.cm2. The I-V curves of the TLMs of p-GaN base layer show significantly improved Ohmic characteristics compared with other reports to date. We attribute the good Ohmic characteristic to the elimination of p-GaN base etching process by using the selective area regrowth method. Calculated by the TLMs I-V curves, the Rs and ρc of the p-GaN base layer is about 88.9 KΩ/sq and 5.22×10-6 Ω.cm2, respectively. The fabricated AlGaN/GaN HBT, which emitter area is 60×60 μm2, with regrown n-AlGaN emitter is characterized by an Agilent B1500A power device analyzer at room temperature. In Gummel plot graph, IB and IC cross over at 400 μA and VBE=5.5V. Beyond the cross-over point, the DC current gain (β=IC/IB) reaches the maximum value of 7 at VBE =13 V. When the VBE exceed 13 V, the IC and IB are saturated. The likely reason is that the Joule heating causes the SHBT performance degradation. The common-emitter characteristics are measured. The applied bias covers a range from 0 to 20 V and the base current varies between 0.5 and 1.1 mA with 600-μA steps. A maximum JC of 2.34 kA/cm2 is achieved at VCE = 13 V. A d.c. power density of 45 kW/cm2 is also achieved at VCE= 20 V. This essey shows an AlGaN/GaN HBT with select-area regrown n-AlGaN emitter, whith has a significantly improved Ohmic characteristics compared with the HBT with emitter etching process [7]. Therefore, it is clearly that using the selective area regrowth method is beneficial to achieve high freqency HBT. In additional, the HBT exhibits d. c. current gain (β) =7, and Jc=2.34KA/cm2 at VCE=13V, which is obviously better than the other select-area regrown emitter HBTs reported before [6]. However, there is great potential for the device through optimizing the interface quality between the p-GaN base and the regrown n-AlGaN emitter layer. Acknowledgements The research is support by the National Natural Science Foundation of China (Grant No. 61674143, Grant No. 61376090 and No. 61474102) and the National Key R&D Program of China. References [1] Yi-Che Lee, Yun Zhang, Zachary M. Lochner, Hee-Jin Kim, Jae-Hyun Ryou, Russell D. Dupuis, and Shyh-Chiang Shen, GaN/InGaN heterojunction bipolar transistors with ultra-high d.c. power density (>3 MW/cm2), Phys. Status Solidi A 209, No. 3, 497–500 (2012). [2] Y. T. Tseng, C. W. Lin, W. C. Yang, K. Y. Chen, and K. Y. Cheng, Influence of Al/Si Codiffusion on Current Gain Deterioration in AlGaN/GaN Single Heterojunction Bipolar Transistors, IEEE Transactions on Electron Devices, 63, 11, 4262-4266, (2016). [3] Y. Zhang, J.-H. Ryou, R. D. Dupuis, and S.-C. Shen, in the Technical Digest of 2008 Int. Conf. on Compd. Semicond. Manuf. Technol., Chicago, IL, April 2008, pp. 257 [4] Y.-C. Lee, Y. Zhang, H.-J. Kim, S. Choi, Z. Lochner, R. D. Dupuis, J.-H. Ryou, and S.-C. Shen, IEEE Trans. Electron Devices 57, 2964 (2010). [5] Lee S McCarthy, P Kozody, M Rodwell, S DenBaars and U K Mishra, First demonstration of an AlGaN/GaN heterojunction bipolar transistor, 25th Int. Symp. Compound Semiconductors, Nara, Japan, 12-16 October 1998. [6] Ajay Raman1, Christophe A. Hurni2, James S. Speck2, and Umesh K. Mishra, AlGaN/GaN heterojunction bipolar transistors by ammonia molecular beam epitaxy, Phys. Status Solidi A, 209, 1, 216-220, (2012). [7] Yi-Che Lee, Development of III-nitride transistors: heterojunction bipolar transistors and field-effect transistors[D] Georgia: Georgia Institute of Technology, 30-39, (2015).

Resume : The GaN gate injection transistor (GIT) bidirectional switches have been demonstrated at the low on-resistance, the normally-off and the functionable operation due to the two p-type gate terminals. In this study, we introduce the temperature dependence into the equivalent circuit model for GaN GIT bidirectional switch by investigating the switching characteristics at the high temperature. The device temperature is varied from room temperature to 100ºC. The parameters of Cg1s1, CR and CD are extracted by the switching waveforms measured the inductive-load chopper circuit. The circuit condition for the parameter extraction is the supply voltage of 200V, the load current of 10A and the gate resistance RG1 of 26Ohm. By investigating the current-voltage Is2s1-Vg1s1 curves obtained from switching waveforms, it is found that the threshold Vth at 100ºC increases as compared with that at room temperature when the device temperature increases. Therefore, the temperature dependence of Vth is employed into the parameter of Ich. By employing the temperature dependence of Vth into the Ich parameters, the calculated waveforms of Is2s1 and Vg1s1 agree well with the experimental ones. And, the calculated switching loss is improved from 3.46x10-4J to 3.71x10-4J, which is almost as same as the experimental switching loss of 3.74x10-4 J. Therefore, the accuracy between the switching loss of calculated results and the experimental ones is improved over 90% by including the effect of the Vth shift.

Resume : AlGaN/GaN HEMTs have been shown to have low on-state resistance and high breakdown characteristics because of the high electron mobility and high breakdown field in GaN-based materials. They are attractive as high-power switching devices and high-frequency power amplifiers. However, dynamic on-state resistance and current dispersion are the key problems that have limited the applications of such devices. The causes of these problems are attributed to the surface states and defects in the epitaxial layers. There are many nondestructive tests to justify the quality of epitaxial wafers. However, it is important to have the primary indicators of wafers before device design and fabrication to obtain the best performance of device for required specification. In this paper, we investigate the characteristics of AlGaN/GaN epitaxial wafers with correlation to device performance to determine the major indicators of wafer. Two AlGaN/GaN HEMT epitaxial wafers (wafer-A and wafer-B) on low-resistivity Si (111) substrates from NTT Advanced Technology Corporation (NTT-AT) with the same epitaxial layers except growth conditions in GaN buffer and channel layers were investigated. The epitaxial wafer is consisted of a 3.9 micrometer carbon-doped GaN buffer layer, ~300 nm GaN channel layer, 1 nm AlN spacer layer, 20 nm AlGaN barrier layer, and 5 nm GaN cap layer. Wafer-B was grown under the growth conditions to reduce the YL/BE value. The evaluations of GaN epitaxial wafers include PL spectroscopy for YL/BE and BL/BE values, SIMS analyses of carbon concentration, XRD and Hall measurements. The YL/BE values at room temperature for wafer-A and wafer-B are 0.0418 and 0.0309, respectively. The BL/BE values at room temperature for wafer-A and wafer-B are 0.0094 and 0.0043, respectively. Both YL/BE and BL/BE values in wafer-A are higher than in wafer-B as growth conditions dedicated. The carbon concentration from SIMS in wafer-A is 2.5 times higher than wafer-B. Higher carbon concentration is consistently observed in GaN epitaxial wafer with higher YL/BE values. According to X-ray rocking curve measurements, the FWHM values of the wafer-A are 571.2 and 566.7 arcsec for the symmetric (002) and asymmetric (102) peaks of GaN. In wafer-B, 578.0 arcsec and 614.5 arcsec were measured for the symmetric (002) and asymmetric (102) peaks. Not a significant increase in FWHMs is observed in wafer-B for all types of defects. The 2DEG mobility and density by Hall measurement at room temperature are 1990 cm2/Vs and 9.039E12 cm-2 for wafer-A and 2040 cm2/Vs and 8.348E12 cm-2 for wafer-B. The sheet resistances are 346.9 and 366.1 Ohm/sq for wafer-A and wafer-B, respectively. Based on the data from nondestructive test, it is difficult to justify the quality of AlGaN/GaN wafers. Therefore, basic Schottky gate HEMTs and simple test structures are implemented to support the test data on wafers. All devices using wafer-A and wafer-B were fabricated in the same layout and process flow. Dry etching by BCl3 and Cl2 mixed gas was used for mesa depth of 450 nm. The ohmic metal used was Ti/Al/Ti/Au (25/125/45/55 nm), and it was first evaporated using E-beam evaporation and annealed at 850C for 40 s to form a low contact resistance. The Schottky gate metal was obtained by evaporating a Ni/Ti/Al/Ti/Au stack (30/25/250/25/200 nm) through E-beam evaporation. There is no field-plate design in this process. All the devices under test are with a gate–source distance of 4 micrometer, a gate length of 2 micrometer, a gate-drain distance of 10 micrometer, and a total gate width of 2 x 50 micrometer. Finally, devices were passivated with 200-nm SiN layer by inductively coupled plasma CVD at 200C. The horizontal I-V characteristics between ohmic contacts (mesa depth of 450 nm) with difference distances show improved leakage characteristics in wafer-B. The vertical I-V characteristics between ohmic contact on the surface and Si substrate show significant increase in breakdown voltage (at 1 A/cm2) from 679 V in wafer-A to 1175V in wafer-B. However, higher leakage current was observed in wafer-B while voltage is lower than 100V, which means a different leakage mechanism in the buffer layer. Consequently, devices fabricated from wafer-B show slightly higher breakdown voltages though on-state I-V characteristics are similar. Moreover, thermal resistances extracted from on-state I-V characteristics under different temperatures for devices from wafer-A and wafer-B are similar while power density is low. If power density is higher than 5 W/mm the thermal resistance of device from wafer-A increases significantly by three times. Pulsed Ids-Vds were measured by Keysight B1525A with pulse width of 50 micro-sec and period of 1 ms. The quiescent bias points of (Vgs, Vds) are (0, 0), (-7, 10), (-7, 20), (-7, 30), (-7, 40) V. Less current dispersion was observed in devices from wafer-B. The different quiescent bias points were used to investigate the effect of off-state bias on transient Ids. The transient Ids decreases with higher drain bias stress from 10 to 40 V. But improvement is observed in devices from wafer-B. The current collapse ratio is improved by almost two times. Furthermore, a detrapping transient of Ids (drain current) was measured under different temperatures by applying an off-state bias of Vds = 50V and Vgs = -7V for 1-s then switching to an on-state bias of Vds = 1V and Vgs = 0V. The current recovers with a major time constant which depends on temperature and is thermally activated with activation energy (Ea). The Ea values can be extracted from Arrhenius plot and are 107 meV and 32 meV for devices from wafer-A and wafer-B, respectively. Though shorter time constants and lower Ea value are observed in devices from wafer-B, but both Ea values at the energy level < 100 meV are interpreted as nitrogen vacancies or surface defects. This measurement demonstrates the importance of surface passivation and filed plates in AlGaN/GaN HEMTs to alleviate the effects of the surface states. Therefore, it is important to evaluate the effects of buffer-related trapping by backgating bias conditions or simple test structures in this study. By backgating bias conditions, applying an off-state bias of Vds = Vgs = 0V and Vsub = -100V for 1-s then switching to an on-state bias of Vds = 1V and Vgs = 0V, in which trapping mostly occurs in the buffer, it is possible to observe detrapping transient of Ids under different temperatures. The extracted Ea values are 420 meV and 364 meV for devices from wafer-A and wafer-B, respectively. Lower Ea value was observed in devices from wafer-B though the difference is limited and interpreted as C/O/H impurities in nitrogen substitutional position. Moreover, by using a simple test structure, a device layout without gate electrode, it is possible to extract the effect (Ea) of buffer-related trapping. The detrapping transients of Ids measured at Vds = 0.5 V right after the on-state stress (Vds = 10 V) for 20 s under different temperatures. The extracted Ea values are 300 meV and 520 meV for devices from wafer-A and wafer-B, respectively. Once again, different Ea values were obtained for two wafers due to different growth conditions in buffer and GaN channel layers. But here using a simple test structure, the extracted Ea in wafer-B is larger than in wafer-A. The possible reason is the mechanisms of detrapping transient of both measurements are different because backgating bias is from off-state to on-state bias while simple test structure is using from on-state to off-state bias. In summary, PL spectroscopy for YL/BE and BL/BE values, SIMS analyses of carbon concentration, FWHMs of XRD (002) and (102) peaks and Hall measurements were used to appraise characteristics of AlGaN/GaN epitaxial wafers. DC I-V, pulse I-V characteristics, breakdown characteristics, and different current transient measurements are implemented on fabricated HEMTs. Based on the device performance in breakdown characteristics, current dispersion, and transient behaviors, only good FWHMs of XRD (002) and (102) peaks are not enough to justify wafer quality. Both YL/BE and BL/BE values would be the good combined indicators for device performance requirements with FWHM values within the acceptable range.

Resume : AlGaN/GaN heterostructure field effect transistors (HFETs) have attracted increasing attention due to the advantages in RF and high-power applications. The device reliability is critical to commercialization. Temperature-dependent measurement [1] was one of the mostly used methods for the reliability analysis, while there were few reports about the low-temperature study on GaN-based HFETs. In this paper, we investigated the C-V characteristics of AlGaN/GaN heterostructure at 77K. Abnormal negative differential capacitance resulting from inversion layer was observed at off-state, which was owing to the reduced direct recombination at low temperature. The AlGaN/GaN epitaxial layers were grown on sapphire substrates by MOCVD. Hall measurement at room temperature shows a sheet carrier density of 7.2×1012 cm-2 and a mobility of 2105 cm2/V·s. Both Ti/Al/Ni/Au Ohmic contacts and Ni/Au/Ni Schottky contacts were fabricated by lift-off process. Ohmic contact resistance of 0.33 Ω·mm and sheet resistance of 455 Ω/□ were achieved after rapid thermal annealing at 840 °C in N2 for 30s. C-V tests of AlGaN/GaN heterostructure were carried out at room temperature (300K) and liquid nitrogen temperature (77K), respectively. The C-V curves were measured at 300 K and 77 K with frequency at 100 KHz. Compared with the room temperature results, the C-V curve at 77 K showed a positive shift of 0.15 V and a decrease in accumulation capacitance. Moreover, the most important phenomenon was that negative differential capacitance was observed at 77 K for AlGaN/GaN heterostructure biased at off-state, which was absent from the previous reports about GaN-based HFETs. The depth of depletion layer as a function of voltage was plotted. The maximum depletion depth for heterostructure at 300 K was ~0.71 μm, pretty deep into GaN buffer layer, while the maximum value at 77 K was only 0.24 μm, and then the depletion depth decreased with the further decrease in gate voltage. The decrease in depletion depth was obviously unreasonable, indicating the depletion model [2] did not any longer apply to this case. In order to explain the negative differential capacitance at low-temperature, the schematic band diagrams of AlGaN/GaN heterostructures biased at different regions were illustrated. At accumulation region, electrons were confined in the triangle-like potential well at heterojunction interface, forming high density of 2DEG. As gate voltage decreased, the band bending became weaker, and the 2DEG was depleted gradually. Further depletion evened the energy band at GaN surface and then bended it upward, leading to the drift of electrons from heterostructure interface to GaN buffer layer and opposite drift direction for holes. When the Fermi level at heterojunction interface was below Ei, inversion layer was formed, resulting in the off-state negative differential capacitance. However, GaN is direct-gap semiconductor and the background electron concentration in GaN was usually in high level (~1017 cm-3), which leads to the remarkable direct recombination and therefore a quiet short lifetime of minority carriers (holes). Because of the direct recombination, inversion phenomenon is barely observed in AlGaN/GaN structures, while at low temperature, the direct recombination rate decreases, resulting in the increase in hole lifetime and inversion at the heterojunction interface. The frequency-dependent C-V results at 77 K were then analyzed. As the measurement frequency increased from 50 KHz to 2 MHz, some inversion carriers with small drift velocity were unable to follow the ac signal. The electrons at the edge of depletion layer were able to follow the ac signal thereby expanding the maximum width of depletion layer in GaN (Wmax) [2]. This also resulted in a more negative inversion voltage and less net inversion charges with an increase in frequency. Quantitative dependence of inversion phenomenon on measurement frequency was also achieved by numerical fitting. At inversion region, the maximum possible time for holes drifting from the edge of depletion layer to the heterostructure interface was defined as τ=1/2πf. Wmax was derived extracted from C-V results. The abnormal experimental data measured at 2 MHz was attributed to the high-frequency series inductance effects on the C-V tests. In this paper, AlGaN/GaN Schottky diodes were fabricated and the C-V characteristics at room temperature and low temperature were investigated. At 77 K strong inversion was achieved owing to the markedly reduced direct recombination compared with the case at 300 K. Strong inversion explained the abnormal negative differential capacitance phenomenon observed at off-state, which was highly dependent on the measurement frequency. References: [1] S. Yang, et al., “Mapping of Interface Traps in High-Performance Al2O3/AlGaN/GaN MIS-Heterostructures Using Frequency- and Temperature-Dependent C-V,” in IEDM Tech. Dig., pp. 6.1.1- 6.3.4, Dec. 2013. [2] D. K. Schroder, Semiconductor material and device characterization, 3rd edition, New York: John Wiley & Sons, 2006, pp. 321-326. [3] O. Ambacher and V. Cimalla, “Polarization Induced Effects in GaN-based Heterostructures and Novel Sensors,” in Polarization Effects in Semiconductors From Ab Initio Theory to Device Applications, edited by C. Wood and D. Jena, New York: Springer Science Business Media, 2008, Chapter 2, pp. 27-110.

Resume : The interface treatment processes for GaN-based MOS-HEMTs have attracted increasing attention due to the great effects on device performance and reliability. Plasma treatment and wet cleaning methods were proved to effectively reduced the interface states, and PMA treatment led to the decrease in interface fixed charges. In this paper, a novel interface treatment process, diffusion-control surface plasma oxidation (DC-SPO) was studied in AlGaN/GaN MOS-HEMTs. The DC-SPO resulted in a decrease in C-V hysteresis from 0.1 V to a negligible level (<10 mV), and a positive shift of threshold voltage Vth from -8.3 V to -5.4 V, indicating the effectively reduced shallow and deep level interface charges, respectively. The AlGaN/GaN epilayers used in this paper were grown on SiC substrates by MOCVD. Both Ti/Al/Ni/Au Ohmic contacts and Ni/Au/Ni gate contacts were fabricated by lift-off process. Prior to the gate fabrication, 10 nm Al2O3 gate dielectric was deposited using ALD. The process sequences for Al2O3 deposition was as follows: in situ plasma nitridation treatment for 5 min, deposition of 1 nm Al2O3 interfacial diffusion layer, plasma oxidation at 300 °C for 30 min, and deposition of 9 nm Al2O3. According to Deal-Grove theory, the surface oxidation of (Al)GaN in this case is diffusion-controlled, with much slower oxidation rate and superior interface quality, compared with the reaction-control oxidation without interfacial diffusion layer. The samples with 10 nm Al2O3 deposition following plasma nitridation treatment were also fabricated for comparison. HR-TEM analysis showed that the DC-SPO resulted in the crystal interfacial Al2O3 layer and the followed high-quality deposition of dielectric layer, while the Al2O3 dielectric layer without DC-SPO was amorphous. C-V measurement showed an increase in accumulation capacitance from 197 nF/cm2 to 243 nF/cm2 by DC-SPO, due to the increased film quality and dielectric constant of Al2O3. The reduced shallow interface states led to a decrease in voltage hysteresis from 0.1 V to a negligible level less than 10 mV. The DC-SPO treatment also effectively reduced the interface fixed charges, which caused the positive shift of Vth from -8.3 V to -5.4 V. In addition, two slopes in C-V curves were observed for the sample without DC-SPO, while only the slope at negative voltage was observed for the case with DC-SPO. In traditional sample (without DC-SPO), the 2DEG at heterostructure interface will overflow into AlGaN barrier layer with voltage above 0V, causing the increase in total capacitance (the second slop in C-V curves). The carrier accumulation at Al2O3/AlGaN interface leads to the second plateau of C-V curves, with capacitance of 10 nm Al2O3 dielectric ~376 nF/cm2. However, for the devices with DC-SPO, the second slope and plateau were not observed, even with gate voltage as high as 10 V. This is because that, the DC-SPO treatment remarkable reduced the interface charges, which raises the energy band of AlGaN barrier layer, and then prevent the 2DEG from overflowing. In conclusion, the novel DC-SPO treatment was used to have effectively improved the interface quality of AlGaN/GaN MOS-HEMTs in this paper. Crystal Al2O3 dielectric was observed and both shallow and deep interface charges were effectively reduced. DC-SPO is a promising interface process method for GaN-based MOS-HEMTs.

Resume : Recently, GaN FinFETs or tri-gate HEMTs have drawn considerable attention because of their potential advantages over planar HEMT. Better suppression of short channel effects (SCEs) from enhanced gate control of additional sidewall gates and possible higher electron velocity would enable further scaling of the gate length for high-speed device application. To date, adoption of varied FinFET configurations is reported in the literatures, but differing in some device behaviors. In particular, with regard to the linearity characteristics, Azize et al. reported a broader transconductance curves (Gm) in a FinFET featuring nano-fins along the entire area between source and drain, whereas better results are achieved by forming fins in a self-aligned way. Very recently, high linearity of intrinsic fT is demonstrated, despite an inadequately linear extrinsic Gm. Thus, a direct comparison between these structures is required in order to not only get more insight into properties of GaN FinFETs but determine the optimal FinFET configuration. In this work, we have performed a comprehensive study of GaN FinFET with varied architectures. It is found that fully-covered fins by gate electrode are of fundamental importance for device performance. FinFET with a field-plate T-gate exhibits an extremely highly linear transconductance behavior as well as high linearity of frequency response. Combined with some superior intrinsic properties of tri-gate structure, the optimized FinFET delivers a 2.1X higher output power density with significant improvement in linearity characteristics despite a 1.6X higher current density. The results indicate that GaN FinFETs are highly suitable for applications such as satellite communication where high power, high linearity and high efficiency are required simultaneously.

Resume : The time dependent off-state leakage (TDOL) of GaN HEMT is essentially important for long term reliability of the power system. In this work, we report a novel degradation mechanism for the TDOL in GaN HEMT on silicon substrate. The device under test is a depletion-mode GaN MIS-HEMT on silicon with LPCVD-Si3N4 as the gate dielectric. It is found that the off-state drain leakage current gradually increases with stress time and the behavior is gate bias and temperature dependent, which stems from the negative shift of threshold voltage (Vth) proved by off-state breakdown measurement with drain injection technique. Reported explanations for the negative shift of Vth in GaN HEMT after electric stress mostly focused on the traps above the 2DEG channel, either in the AlGaN barrier layer or at the insulator/semiconductor interface of the MIS gate structure. Hole generation and accumulation under the gate is also another possible mechanism. However, the repeated “stress/measure” test showed that the shift of Vth induced by the traps above the 2DEG channel is marginal. The possibility of hole accumulation could also be excluded since the shift of Vth could not recover in a short time. Alternately, we proposed that the time dependent ionization of the uncompensated donor like deep levels in unintentionally doped GaN layer is the dominant mechanism responsible for the large negative shift of Vth and the TDOL behavior.

Resume : It is well known that Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) are good high-power semiconductor devices because they have high breakdown voltage, high mobility, and large amount of 2DEG due to the polarization field. To operate HEMTs in high voltage, using the field plate to enhance the breakdown voltage of the HEMTs is necessary. In this paper, we studied the different slanted or curved field plates to investigate the influence to the reduction of the peak electric field in the channel. Gates deposited on SiN passivation with a curved sidewall (the slanted or curved field plate) were applied. With this structure, the peak electric field with different voltage will be studied to find the optimized condition. We will examine different configurations of the field plates to see how the geometries of the field plate reduce the peak electric field along the channel. Our preliminary results show that without optimization, the peak electric fields of different configurations are mainly located at the end point of gate toward the drain side and the end point of the slanted field plate at the highest operation voltage. Overall, at VD = 100V, h (which is defined as the minimum thickness of the slanted field plate) = 50nm to 100nm, the concave structure, and convex structure, the concave structure give the better balance of electric field between gate and field plate. However, this depends on the operation voltage we are interested. In addition, the current is also affected for different h. By using a curved field plate, it is possible to increase the breakdown voltage of the device with a more smooth distribution of electric field. It might be difficult to fabricate a curved field plate. However, by controlling the etching angle and selective etching solvent, it might still feasible for future applications. REFERENCES [1] Y. Okamoto, Y. Ando, K. Hataya, T. Nakayama, H. Miyamoto, T. Inoue, M. Senda, K. Hirata, M. Kosaki, N. Shibata, et al., “Improved power performance for a recessed-gate AlGaN-GaN heterojunction fet with a field-modulating plate,” IEEE Transactions on Microwave theory and techniques 52(11), pp. 2536–2540, 2004. [2]S. Karmalkar and U. K. Mishra, “Enhancement of break- down voltage in AlGaN/GaN high electron mobility transistors using a field plate,” IEEE transactions on electron devices 48(8), pp. 1515–1521, 2001.

Resume : AlGaN/GaN transistors are expected for utilization of high power microwave and millimeter-wave applications due to their high carrier density and high electron saturation velocity, and high breakdown voltage. If on-Si technology for AlGaN/GaN transistors can be used, it would be highly cost-competitive to Si-based high frequency transistors such as LDMOS and SiGe. However, a drawback of on-Si technology must be high frequency leakage to the substrate, which inherently occurs due to resistivity of the Si substrate. Only a solution may be a thick buffer between the Si substrate and a channel layer. In this paper, we investigate effect of the AlN/GaN buffer thickness on high frequency leakage in GaN on Si HEMTs. We have successfully grown a thick 1600 nm buffer on a highly resistive Si substrate (> 5000 Ω cm). For comparison, a 300-nm-thick buffer was also prepared. The effect of leakage with the buffer layer was evaluated with an equivalent circuit. The resistance for a pad electrode (90 x 90 μm2) on the buffer layer was estimated to be 15000 and 5000 Ω, respectively. AlGaN/GaN HEMTs with a gate length of 1.5 μm on each buffer layer show the maximum oscillation frequency of 8.4, and 5.6 GHz, respectively. We have confirmed that a thick buffer on the highly resistive Si substrate improves microwave performance of the AlGaN/GaN HEMT on the Si substrate.

Resume : Devices? working frequency increased rapidly with the growing demand on broadband information transmission, personal communication and military confidential communication. Thus comprehensive research on ultra-high frequency GaN HEMTs is necessary. To date, most GaN high frequency HEMTs are based on ternary barrier AlGaN/GaN heterostructure. InAlGaN/GaN barrier reveals stronger polarization effects and higher carrier mobility, thereby promising for higher frequency devices. In this paper, we demonstrate a high performance (fT/fmax of 200/310 GHz) ultra-thin (tbar=8 nm) quaternary InAlGaN barrier HEMTs with a 50-nm gate length. The epitaxial heterostructure was grown on a SiC substrate. It consists of a 7-nm InAlGaN barrier layer, a 1-nm AlN interlayer and an undoped GaN channel layer. Room-temperature Hall measurement exhibits a sheet resistance of 210 ?/sq, a carrier concentration of 1.82×1013 cm-2, and a high carrier mobility of 1627 cm2/V?s. A 50-nm T-shape gate was defined by e-beam lithography and then subsequent Ni/Pt/Au/Pt/Ti (10/30/550/30/10 nm) metal evaporation. Our device shows a high DC drain current density of 2.2 A/mm, a high peak extrinsic transconductance of 823 mS/mm, a high current-gain cutoff frequency of 200 GHz and a high power-gain cutoff frequency of 310 GHz. Besides, a high electron velocity of 1.48×107 cm/s and a parasitic delay of 0.5 ps were obtained. These results reveal huge potential of this quaternary barrier for RF devices applications.

Resume : In this paper, we present that acceptor-like states at insulator/AlGaN interfaces are dominantly responsible to the Vth shift in GaN MIS HEMTs after applying a forward bias stress. We prepared two Al2O3/AlGaN/GaN diode structures without and with the Cl-based ICP etching of the AlGaN surface. The 20-nm Al2O3 was deposited on the AlGaN surface by ALD. The etching depth of AlGaN was 7 nm. Both diodes showed C–V curves with two steps, peculiar to the MIS structure fabricated on the heterostructure. For the ICP-etched sample, we observed the less slope of the C–V curve and the higher on-set voltage at the forward bias regime, indicating the higher electronic state densities at the Al2O3/etched AlGaN interface. Then, the C–V measurement was performed with the bias swing starting from various maximum voltages (Vm). The ICP-etched sample showed significant parallel C–V shifts toward the positive bias direction with increasing Vm. To understand the Vth shift behavior, we carried out numerical C–V calculations, taking into account state density distributions at Al2O3/AlGaN interfaces and the bias swing effect. The calculation quantitatively reproduced the forward-bias dependent Vth shifts. The amount of negatively charged acceptor states (filled with electrons) increases with Vm, because the larger forward bias makes the surface Fermi level closer to the conduction band bottom of AlGaN. The interface control is absolutely necessary for the Vth stability of insulated-gate GaN HEMTs.

Resume : Because the p-GaN formation by ion implantation is known to be technically difficult, p-GaN regrowth technique is very important to demonstrate a GaN power device. In this presentation, I will introduce about the electrical performance of the PN Diode, which is regrown on partially etched n-GaN template without using a mask. As we expected, the leakage of the PN Diode, which was formed on etched n-GaN including a sidewall, was highest. The leakage depends on the growth condition, and we achieved a relatively low leakage PN Diode by adjusting the growth condition. In addition, we investigated several methods for improving the performance of the PN Diode. Then, we realized that the Mg pre-flow treatment just before p-GaN regrowth is the most effective. The property of the PN Diode grown on etched n-GaN including a sidewall with Mg pre-flow treatment is not inferior to that of in-situ grown PN Diode. In the near future, we will demonstrate GaN vertical devices using this regrowth technique.

Resume : Reactive ion etching (RIE) is an indispensable technique in the III-nitride semiconductor device processes. However, ion bombardment in the RIE process introduces structural and electrical/optical damage on the etched surface and, therefore, RIE-GaN surfaces have not been used as active regions in devices. In this paper, we demonstrate that an electron mobility as high as 1350 cm2/Vs is achieved in AlGaN/GaN heterostructures by direct AlGaN regrowth on RIE-processed GaN surface without using regrown GaN layers. As substrates, n--GaN/SiC with a c+-face is used. About 200 nm-thick surface layer of the n--GaN is etched off by RIE with a bias power 30 W. After the substrate is loaded into the MOCVD reactor, it is annealed in the NH3 flow at 850˚C for 15 min. Then, a 30-40 nm-thick AlxGa1-xN (x〜0.3) layer is grown at 950-1000 ˚C using TMA, TMG, and NH3. The sheet carrier density ns obtained for fabricated AlGaN/GaN structures is in the rage of (5-20)x1012 cm-2, which is comparable to that for samples with a thick (≳0.5 μm) regrown GaN. This suggests that N vacancies induced by ion bombardment during RIE process and contamination of donor impurities such as Si and O on the RIE-GaN interface are effectively reduced by the annealing in the NH3 flow just before growth. On the other hand, sheet resistance Rs obtained varies from 2x102 to 1x105 Ω/□, resulting in an electron mobility μ between 1350 and 10 cm2/Vs. The highest value, 1350 cm2/Vs, is obtained with ns =1.7x1013 cm-2 and Rs=270 Ω/□. Thus, 2DEG transport properties comparable to those for samples grown on a thick regrown GaN can be achieved at the regrown-AlGaN/RIE-GaN interface. Measurement temperature dependence of μ and DC characteristics of HEMT devices fabricated using regrown-AlGaN/RIE-GaN systems are also shown in the presentation.

Resume : Threshold voltage instabilities are examined in E/D-mode InAlN/GaN MOS HEMTs with 2 micron gate length and 10 micron source-drain spacing integrated in logic invertor. The technology of E-mode HEMTs is based on highly selective low-damage dry etching of the n++ GaN cap for the gate recessing. The recess is combined with a 10-nm thick Al2O3 grown by atomic-layer deposition (ALD) at 380 K and a metal lift-off in a single lithographic step providing a self-aligned approach. In the D-mode HEMT, the gate recessing is skipped. The nominal threshold voltage (VT) of E/D-mode HEMTs was 0.6 and -2.4 V respectively, with technology invariant maximal drain current of about 0.4 A/mm. Analysis after 580 K/15 min annealing step and at an elevated temperature up-to 430 K reveal almost complementary device behaviour depending on the HEMT operational mode. It was found that the annealing step decreases VT of the D-mode HEMT that was attributed to a reduced electron injection into the modified oxide. On the other hand, VT of the E-mode HEMT increases due to a reduced density of surface donors at the oxide/InAlN interface. Operation at the elevated temperature produces reversible changes: increase/decrease in the VT of the respective D-/E-mode HEMTs. Additional bias-induced experiments exhibit complex trapping phenomena in the devices: Coaction of shallow (~0.1 eV below EC) traps in the GaN buffer and deep levels at the oxide/InAlN interface was identified for the E-mode device; while trapping in the D-mode HEMTs was found to be consistent with a thermo-ionic injection of electrons into bulk oxide traps (~0.14 eV above EF) and trapping at the oxide/GaN cap interface states. This work was supported by the Slovak Research and Development Agency under the contract No. 15-0673.

Resume : Several methods have been used to investigate the mechanisms of the gate leakage current, such as Temperature-dependent gate current-voltage characteristics [1], some special test device structure to separate the components of leakage currents [2], and Electroluminescence measurement [3]. These methods cannot provide the specific spatial distribution of leakage current except to Electroluminescence. However, Electroluminescence measurement is required a large voltage bias and the transparent gate electrode. Electron-beam induced current (EBIC) measurement can be used to investigate the specific location of leakage current paths and the electrical active defect of devices, including the area under the opaque gate electrode at any voltage bias. In this paper, we present the analysis of the EBIC in AlGaN/GaN heterostructure to reveal the characteristics of the gate leakage current in spatial dimension. Epilayers of the AlGaN/GaN heterostructure used in this study were grown on the sapphire substrate by metal-organic chemical vapour deposition. The devices fabrication started with Ohmic contact formed by an alloyed Ti/Al/Ni/Au metal stack annealed, followed by the mesa etched-isolation, SiN passivation and Ni/Au/Ni gate contacts. Owing to no metal overlapping the mesa sidewall, the circular Schottky diode was used to compare the leakage paths with the square Schottky diodes.With the increase of reverse voltage, the reverse leakage current of circular shaped Schottky diodes is trend to be saturated, while the reverse leakage current of square Schottky diodes is gradually increased. It can be inferred that there is an additional electrical leakage path in the square Schottky diodes compared with the circular shaped Schottky diodes. As to the conventional mesa isolation, the gate-pad metal of the square Schottky diodes overlaps the mesa sidewall, which results in the connection of gate-pad metal to the conductive channel of the HEMT. In order to analyze the location of the additional leakage component of the square Schottky diodes, EBIC measurements were performed on both of the mesa type device (square Schottky diodes) and the planar type device (circular shaped Schottky diodes). The EBIC mappings are measured under VGS = 0V and VGS = -5V. It can be seen that the leakage path exists on the mesa edge as for square Schottky diodes when reverse bias voltage applied, and the isolation region also exists the leakage path between the two electrodes. While the leakage path of square Schottky diode is only through the area under the gate. And the inhomogeneous intensity at the gate region reveals the location of defects where leakage current passed through. The EBIC comparison of the two types (mesa and planar) of device reveals that the excessive leakage current exists on the mesa edge and the buffer area between the Schottky and ohmic contacts, which interprets the unsaturated tendency of reverse current in I-V measurement. The spatial distributions of the leakage current in square Schottky diodes with and without SiN passivation layer are measured with EBIC, and the contrast of EBIC mapping presents the intensity of current through the devices when the electron beam acts on the samples. In the EBIC measurements, the square Schottky diodes covered with SiN passivation layer are biased at 0V and -1V. When the negative bias applied on the square Schottky diodes, three different types of leakage paths appeared. Type A leakage path represents the leakage path through the 2DEG channel caused by the overlaps of the gate and the channel at mesa edge, type B leakage path is the leakage path through the interface of SiN and mesa sidewall along the mesa edge, and type C leakage path is refer to the leakage path through the two electrode pads at the isolation region. To further analysis the three types of leakage paths, the SiN passivation of the Schottky diode is removed. The EBIC mapping of the the device without SiN reveals that after removing the SiN, type B and type C leakage paths are disappeared, which proved that the type B and type C leakage paths are caused by SiN passivation. The line profiles of EBIC along the mesa edge of the device biased at -1V. The intensity of the peaks corresponding to the type A leakage paths are higher when SiN is removed. Which results from the more generated electron-hole pairs within the removal SiN device. As the result of the less loss of the electron energy, the interaction between the electron beam and the device at the same region are stronger when the SiN passivation layer is removed, and the generated electron-hole pairs relatively increase at the same electron-beam acceleration voltage. Therefore, the intensity of EBIC in the device without SiN is higher than that of with SiN at the same bias. Meanwhile, once the high energy electrons reach the stronger electrical field region, further being accelerated by the high electrical field. It may result in an avalanche at the mesa edge which overlapped with gate metal. And the electric field strength reach the maximum value at the cross line of the mesa edge sidewall and the AlGaN/GaN interface [8], it will increase the possibility to avalanche. At the position between the Schottky contact and ohmic contact along the mesa edge, the leakage path of the device without SiN passivation disappears compared with that of with SiN passivation. It can be inferred that SiN passivation induced the short circuit between Schottky contact and ohmic contact through the interface of SiN and mesa sidewall along the mesa edge. It should be focused that the EBIC intensity gradually weaken from the Schottky electrode to Ohmic electrode. On account of the electric field gradually decreased from the Schottky electrode to Ohmic electrode, the generated electron-hole pairs closed to the Schottky electrode willl be accelerated to a higher speed than others, and these higher energy carriers then have more opportunity to be collected. And the relative lower energy carries have the possibility to recombine or be capture by the trap along the mesa edge. As we have mentioned above, type C leakage path (the leakage path between the two contact pads at isolation region) is induced by SiN passivation. In order to confirm that the leakage path is caused by the interface of SiN/GaN at isolation region, the different acceleration voltages are used to control the action depth of electron-beam. The type C leakage path disappears with lower acceleration voltage. The simulation of the interaction of electron-beam and SiN/GaN at isolation region with different acceleration energy is used to show the distribution of the generated-electron and the energy distribution of the electrons. As known from the simulation, the generated electrons and high energy electron majorly distribute in the SiN bulk with acceleration voltage of 5keV. As for the acceleration voltage of 10keV, the high energy electron majorly distribute at the interface of SiN/GaN. Therefore, the disappearance of type C leakage path is owing to the generated electrons concentrated in SiN bulk, and these nonequilibrium carries would have more possibility to recombine or be captured because of there is no leakage path to let them escape. It can be concluded that the leakage path of type C is major at interface of SiN/GaN in isolation region. In conclusion, the EBIC measurement is utilized to probe the spatial location of leakage paths of AlGaN/GaN heterostructure. The mesa type device show three addition leakage paths: through the 2DEG channel caused by the overlaps of the gate and the channel at mesa edge, at the interface of SiN and mesa sidewall along the mesa edge and through the two electrode pads at the isolation region. The dominated leakage paths of the device without SiN passivation layer is through the 2DEG channel caused by the overlaps of the gate and the channel at mesa edge, while the one with SiN through the isolation region between Schottky electrode and Ohmic electrode. [1] S. Arulkumaran et al., Appl. Phys. Lett, pp.3110-3112, 2003 [2]Y. H. Chen et al., Appl. Phys. Lett, pp. 3110-3112, 2014 [3] Y. Lu et al., IEEE T-ED, pp. 821-827, 2015.

Resume : Thermal management is one of the key factors for GaN power devices. It has been reported that diamond integration is an effective technique to reduce self-heating and improve the thermal performance of GaN devices, by either incorporating a high thermal conductivity diamond substrate, or adding p-diamond back barrier, or coating device surface with nanocrystalline diamond (NCD). However, these integration methods have shown limitations in extracting heat out of the hottest locations (for example, drain side gate edges) in the devices, therefore, more effective approaches are still missing and is the focus of this work. This work explores p-type doped nanocrystalline diamond (NCD) as gate contact and the corresponding thermal and electrical performance in InAlN/GaN high electron mobility transistors (HEMTs) via simulation. The self-consistent electrothermal simulations are carried out by Silvaco ATLAS, and it reveals that the p-NCD-gated InAlN/GaN HEMT can not only exhibit much better thermal performance but also allow normally-off operation. The conduction band diagram of the simulated p-NCD gated InAlN/GaN HEMT is compared to that of the HEMT without the p-NCD gate. The device dimensions such as the source-to-gate distance, gate foot length and gate-to-source distance, and the heterostructures are otherwise equal. In the simulated device, the p-NCD layer is 100 nm thick with uniform volume doping density of 1×10^20 cm-3, and the gate metal is Pt as Ohmic contact with the p-NCD layer. As shown in this work, the p-type uniformly doped NCD film under the gate lifts the conduction band upwards and depletes the two dimensional electron gas (2DEG) channel, resulting in a positive shift of the threshold voltage Vth. As the p-NCD doping density increases from 1×10^16 cm-3 to 1×10^21 cm-3, the threshold voltage of the p-NCD gated InAlN/GaN HEMT increases from 0.16 to 0.55 V. Additionally, as the high thermal conductivity p-NCD film is in direct contact with the drain side gate edge, which is the hottest place in the device, much enhanced thermal performance is demonstrated. Compared to a device capped with 0.3-μm NCD film but without the p-NCD gate, the p-NCD gated device with the same thickness of NCD capping layer shows ~ 30% lower device peak temperature, at the fixed dc output power of 35 W/mm. In practical applications, the device peak temperature limitation Tlimit of GaN-on-Diamond HEMTs is up to 300 ºC to ensure long term reliable operation. The peak temperature versus output power performance for a GaN-on-SiC HEMT passivated with 1.0-μm Si3N4, a GaN-on-diamond HEMT passivated with 1.0-μm Si3N4, and 1.0-μm NCD passivated GaN-on-diamond HEMTs without and with p-NCD gate are comparatively studied. At a fixed Tlimit of 300 ºC, the NCD capped GaN-on-diamond HEMT with p-NCD gate shows two times enhancement in power density (60 W/mm) than that of the Si3N4 passivated GaN-on-SiC HEMT without p-NCD gate (20 W/mm), and ~28% power density improvement than that of NCD capped GaN-on-diamond HEMT without the p-NCD gate (47 W/mm). The Current gain cutoff frequency (fT,max) as a function of gate length Lg is also simulated and presented, which shows the incorporation of uniformly doped p-NCD gate does not diminish device frequency performance.

Resume : We demonstrate, for the first time, a straightforward carrier mobility measurement technique on ultra-wide band gap 2DEG devices which can be performed following Au/Pt Schottky contact deposition, without the need for the irreversible wafer processing required for Ohmic contact growth and isolation. Using this technique, we measure mobility over an exceptionally wide 2DEG density range from 1E10 to ~1E13 cm-2 at the Al(0.85)Ga(0.15)N/Al(0.7)Ga(0.3)N heterojunction. Peak mobility at room temperature was 154 cm2/Vs, and decreased with temperature to the power -0.8. This is much lower than the -1.5 dependence expected from optical phonon scattering and closer to the -0.5 power expected from alloy scattering. Ultra-wide band gap heterojunctions enable higher breakdown voltage and lower specific on resistance capability than the more common AlGaN/GaN devices [1], however mobility may be a performance limiting factor. The structure studied consisted of a barrier layer of 40nm Al(0.85)Ga(0.15)N:Si ~1e18 cm-3, grown on a buffer of 550nm UID Al(0.7)Ga(0.3)N regrown on an AlN/sapphire template. Our technique differs from established methods [2] by utilising measurements of dispersion only via capacitively coupled disc and surrounding annulus Schottky contacts to the 2DEG. References: [1] Hudgens, J., IEEE Trans. Power Electronics, vol. 18, no. 3, May 2003. [2] W. M. Waller, et al, IEEE Trans. Elec. Dev., vol. 63, pp. 1861-1865, May 2016. © British Crown Owned Copyright 2017/AWE

Resume : High-k dielectrics are increasingly employed in normally-ON and normally-OFF AlGaN/GaN transistor architectures for better channel electrostatics and gate leakages. However, the presence of such a dielectric adds another interface and hence more complexity to a system where interfacial properties are key to device operation. For example, commonly used Al2O3 dielectrics have a positive fixed charge density of 4.6e12 cm-2 leading to large threshold voltage shifts of the fabricated devices, and impacting reliable operation. E-beam evaporated HfO2 is shown to be a facile gate dielectric for the technologically important GaN-on-Si platform. Electrical properties of HfO2 with both GaN directly, towards normally-OFF device architectures, and with the AlGaN barrier for normally-ON AlGaN/GaN MISHEMTs are investigated in depth. A conduction band offset of 1.9 eV and peak Dit of 6.2e12eV-1cm-2 was extracted for HfO2/GaN, with no shift in the flat band voltage with dielectric thickness indicating minimal fixed bulk and interfacial charges. Normally-ON HfO2/AlGaN/GaN MISHEMTs exhibit negligible shifts in threshold voltage, transconductance of 120mS/mm (Lg=3μm) and OFF-state gate leakage of 20-50nA/mm (at Vd=100V). The AlGaN/GaN interface shows two conductance peaks corresponding to slow and fast trap states with peak Dit values <5e13eV-1cm-2 while the HfO2/AlGaN interface has a peak Dit of 3.7e13 eV-1cm-2 at 0.41eV below EC, unchanged with gate voltage, suggesting a good quality interface.

Resume : During the past decades, the surface acoustic wave filters (SAW) based on LiNbO3 have been widely applied on front-end radio frequency modules for mobile communications devices. At present the operating frequency of LiNbO3 is below 2GHz [1] due to lower velocity (3400-4000 m/s) and restricted photolithography precision for smaller finger and finger interdigit spacing. At present there is a huge demand for SAW devices with a working frequency above 2GHz. The AlN-based SAW resonators are very promising for GHz resonance frequency (above 2 GHz) due to high sound velocity (5500-6200 m/s), good piezo-electric properties and excellent temperature stability, which makes AlN-based SAW devices have become a research hot. Usually the AlN films for SAW devices are based on magnetron sputtering technology [2-4] or grown by Metal-organic Chemical Vapor Deposition (MOCVD) method [5-6].However, the research of the influence of AlN materials crystal quality on the resonators’ characteristics is relatively rare. In our experiments, we prepare two kinds of AlN films on the sapphire substrate with Metal-organic Vapor Phase Epitaxy (MOVPE) and sputtering methods at the first time, then the SAW resonators are manufactured with the same process fabrication. The resonators include an interdigital transducer (IDT) and a pairs of reflectors. The IDT consists in 100 pairs of fingers formed by 4 um width metal strips separated by 4 um, and each reflector has 250 pairs of fingers with a 4 um wide fingers/finger interdigit spacing. The value of operating frequency for MOCVD AlN SAW devices and sputtering AlN SAW devices are respectively about 347.2MHz and 345.5MHz, exhibiting a 0.5% increasement in sound velocity for AlN SAW resonators based on MOCVD methods. The effective electromechanical coupling coefficient （K2eff） for MOCVD AlN SAW and sputtering AlN SAW resonators are respectively about 2.8% and 2.5% ,showing a 5% improvement for MOCVD AlN SAW resonators which means AlN films based on MOCVD methods have better piezo-electric characteristics. In conclusion, the better operating performance for the AlN films based on MOVPE technology can be attributed to higher crystal quality and lower surface roughness, which means that AlN materials preparation by MOCVD have excellent crystal quality and AlN SAW based on MOCVD are promising in obtaining high-performance resonators. References: [1] Stefanescu A, Müller A, Giangu I, et al. Influence of Au-Based Metallization on the Phase Velocity of GaN on Si Surface Acoustic Wave Resonators[J]. IEEE Electron Device Letters, 2016, 37(3): 321-324. [2]. Kirsch, P., M. Assouar, O. Elmazria, et al., 5GHz surface acoustic wave devices based on aluminum nitride/diamond layered structure realized using electron beam lithography. Applied physics letters, 2006. 88(22): p. 223504. [3]. Rodríguez-Madrid, J., G. Iriarte, D. Araujo, et al., Optimization of AlN thin layers on diamond substrates for high frequency SAW resonators. Materials letters, 2012. 66(1): p. 339-342. [4]. Rodriguez-Madrid, J., G. Iriarte, J. Pedros, et al., Super-high-frequency SAW resonators on AlN/diamond. IEEE Electron Device Letters, 2012. 33(4): p. 495-497. [5]. Kaya, K., H. Takahashi, Y. Shibata, et al., Synthesis and Surface Acoustic Wave Properties of AlN Thin Films Fabricated on (001) and (110) Sapphire Substrates Using Chemical Vapor Deposition of AlCl3–NH3 System. Japanese journal of applied physics, 1997. 36(5R): p. 2837. [6]. Uehara, K., H. Nakamura, H. Nakase, et al. AlN epitaxial film with atomically flat surface for GHz-band SAW devices. in Ultrasonics Symposium, 2002. Proceedings. 2002 IEEE. 2002. IEEE.

Resume : A recessed-gate structure is promising for the normally-off AlGaN/GaN high-electron-mobility transistors (HEMTs), in which the top part of AlGaN layer should be etched just on the designed thickness. To achieve high stability and high performance of the HEMT, a damage-free etching process with good controllability is required. In this study, we aimed to develop the low-damage etching process for AlGaN layers using a photo-electrochemical (PEC) reaction. We used the AlGaN/GaN heterostrcuture grown on the Si substrate with AlGaN-barrier thickness of 25 nm. The PEC etching was conducted in the acid-based electrolyte by using a SiO2 film as an etching mask under UV-light irradiation. The etching condition was drastically changed with both the light wavelength and its irradiation power. Under the optimal condition, the etching-rate of 0.12 nm/min was achieved, leading to the relatively smooth surface with an rms-roughness of 0.4 nm. The I-V and C-V characteristics of Schottky contacts formed on the etched AlGaN surface showed ideal behavior, in which the low-leakage currents and good-gate control were obtained. The threshold voltage of AlGaN/GaN HEMT was shifted from -2.42 to +0.20 V by applying the PEC etching of 17 nm for the recessed-gate structure. In addition, transconductance, gm, of the recessed-gate HEMT showed larger value than that of the planar-gate HEMT. The PEC etching is very attractive for the normally-off operation in AlGaN/GaN HEMTs without any processing damage.

Resume : AlGaN/GaN high electron mobility transistors (HEMTs) extensively used in various applications, such as high power, high frequency and high power switching devices.

Resume : Manipulation of charges at the oxide/III-N interface in MOS heterojunctions represents a promising approach for controlling the gate-stack scaling properties. However, the origin of the interface charges is not understood to date. In this work, we systematically analysed the impact of various pre-treatments (no, HCl, and HCl followed by ex-situ O-plasma exposure) applied prior to MOCVD growth of Al2O3 at 600 °C and post-deposition annealing (PDA, 700 °C, 1 hour, N2) on the net interface charge (Nint) in MOS-HEMT gate junctions. Nint was determined using CV measurements on the Al2O3/GaN/AlGaN/GaN structures with varying Al2O3 thickness. It was found that all pre-treatments result in relatively large negative Nint of density ranging from 0.8 to 1.1×1013 cm-2. Subsequent PDA led to reduction in Nint (no pre-treatment) or change into positive charge with density in the level of 2 to 3×1012 cm-2 (HCl, HCl and O-plasma). While negative Nint most likely originates from the III-N surface polarization charges, the effect of PDA can be understood as a result of compensating charge formation, often referred to as surface donors. Our data therefore indicate natural tendency of the oxide/III-N interface towards charge compensation upon high-temperature treatment. The results will be further discussed in conjunction with high-resolution TEM and XPS analyses. This work was supported by project SAFEMOST funded by V4-Japan initiative and the Slovak R&D Agency under contract No. 15-0031.

Resume : In this work, we investigate the feasibility of using NH3-MBE technique for the monolithic integration of GaN HEMTs with Silicon MOS devices in a CMOS-first scheme. By avoiding the introduction of GaN in the Silicon CMOS line, such a scheme may be a more acceptable way for Si industry requirements. In order to limit the detrimental effects of high growth temperatures on MOS structures, the thermal budget of NH3-MBE growth processes used for the fabrication of AlGaN/GaN heterostructures was minimized as much as possible with regards to their structural and electrical properties. More, this new low-temperature process (< 850 °C) allowed the development of a selective area growth process and helped to prevent contamination issues in nitrides layers, as previously reported when using masking materials such as SiO2 at high temperature (> 900 °C). We observed that delamination may occur in MOS areas for thick GaN structures (> 1 µm). To avoid delamination, we developed an original solution by inserting a low-temperature GaN layer in the masking stack which provided the advantage of a quasi-spontaneous lift-off of GaN grown on the CMOS area without degradation of the underlying protection films. Finally, the degradation induced by such NH3-MBE growth processes on MOS structures was assessed through electrical measurements and diffusion length determination in source and drain regions of NMOS devices.

Resume : Due to their promising features such as a wide band-gap, high saturation electron velocity and high 2-D electron gas density, AlGaN/GaN high electron mobility transistors (HEMTs) have gained increasing attraction in RF applications, making this technology very attractive for telecommunication, defence and satellite communication applications. In recent years power amplifiers have been established to provide high power levels not achievable with other technologies. Advances in scaling and performance of GaN based HEMTs exhibit great potential for industrial use in high-frequency applications up to W-band frequencies and above. Further performance enhancement, especially in the higher frequency bands, must come along with the improvement of the epitaxial structure and reliability. This paper reports the development of an European short gate-length technology for GaN HEMTs and MMIC processes at Fraunhofer IAF. Critical development tasks are the supply chain for epitaxial structures and beside small dimensions, the definition of the gate. Therefore, a stable and reliable gate process with lg = 100 nm is used to evaluate optimized epitaxial structures. Additionally, gate concepts like T-gates, spacer or SiN-assisted gates are compared and evaluated in terms of performance and reliability. The main purpose of this development is to facilitate a reliable European process with an intended lifetime of more than 108 h. Measurements exhibited improved voltage ruggedness and therefore increased output power, by varying the gate module and/or the gate metallisation. The degradation of the saturation current was decreased by more than 3 orders of magnitude by an improved gate module for W-band transistors with fmax exceeding 130 GHz.

Resume : Trapping effects in AlGaN/GaN HEMTs present a major limitation on the power performance at high frequencies and the dynamic performance, for the density of 2DEG is altered by the electrical charge trapped in the bulk and/or on the surface. Deep level transient spectroscopy(DLTS), as one rapid, sensitive, and straightforward technology, has been utilized in GaN-based devices since 1994. Three main native traps have been introduced: 0.15-0.26 eV [1,2]，0.5-0.61 eV [3,4] and 0.67-0.89 eV [4,5] , which are related to nitrogen vacancy, nitrogen antisites and nitrogen interstitials, respectively. The traps with responding to dopants have been investigated by some groups. C doping will introduce a new trap with energy of Ec-0.4eV (CGa) and reduce the concentration of NGa. [6] A. Sasikumar et al. [7] reported that the Ec-0.45eV trap was the dominant electrical stress-affected trap and likely caused the HEMT drain-lag and increased the mild knee-walkout. Deep levels induced by electron irradiation[8] and proton irradiation[9] have been investigated. In this study, DLTS measurements have been applied to AlGaN/GaN heterostructure with various reverse voltages, filling pulse voltages and width. Hole-like traps are detected and related to surface states that impact on DLTS signals of other electron traps. The AlGaN/GaN hetero-junction structure used in this paper was grown by MOCVD on (0001) sapphire substrates. The epitaxial structure was composed of, from the substrate up, a nuclear layer, a 1.3 μm unintentionally doped (UID) GaN layer, a 1nm thick AlN interlayer and a 20 nm thick unintentionally doped Al0.3Ga0.7N barrier layer. Circular shaped Schottky diodes were utilized for CV, IV and DLTS measurements with circular gate contact having a diameter of 130 μm and surrounding ohmic contact with an Ohmic-Schottky separation of 30 μm. CV and IV characteristics were measured at room temperature in the dark to characterize the devices and determine the voltage range applied in the DLTS measurements using Semetrol Deep Level Transient Spectroscopy system. The frequency of CV and DLTS measurement was 1MHz. The temperature range was from 45K to 450K in DLTS measurement. DLTS spectra was measured in the pinch-off region (Vr = -3 V, Vf = -2 V, pulse width=0.1 ms). The main capture and emission processes take place in the AlGaN/GaN interface under present bias condition according the CV curve. One electron trap around 300K is detected and the trap energy is Ec-0.56 eV and the capture cross section is 7×10-15 cm-2, which has been considered to be nitrogen antisites. [5] The pulse width dependence of the transient capacitance amplitude at 300K shows that the amplitude related to positive DLTS signal (electron trap or majority trap signal) decreases as the pulse width gradually increases until 0.4ms, and the negative signal arises and the amplitude increases as pulse width larger than 0.4ms, which may be caused by overlapping multiple traps. Partial charges are emitted from the trap with active energy of Ec-0.56 eV, as the filling width becomes larger than its typical emission time constant, which contributes to the decreasing amplitude of electron-trap signal. DLTS scan with 50ms filling pulse and the same voltage setting (Vr = -3 V, Vf = -2 V) shows obvious two negative peaks H1 and H2 corresponding to trap energy of EV+0.47 eV, capture cross section of 1.2×10-14 cm-2 and EV+0.10 eV, capture cross section of 4.9×10-21 cm-2, respectively. The negative peaks are not likely corresponding to the change in hole-trap states in the bulk, for the hole traps in the bulk are usually occupied by electrons and could not contribute to the capacitance transient. What is more, holes can hardly generate in the bulk under present bias condition. The hole-like trap signal can be explained by the variation in the population of surface states occupied by electrons. Electrons injected from gate are captured by surface states and depletion layer under ungated surface extends to steady position just before the filling pulse. The change in population of surface states, which are occupied by electrons before filling pulses, emit electrons during filling pulse, and re-capture electrons after filling pulse, results in a change in 2DEG density due to the charge neutrality, and consequently contributes to capacitance transient performance. When the gate switches to filling pulse, gate depletion shrinks instantaneously, while the depletion region under ungated surface cannot respond to gate voltage immediately, for it takes longer time to emit electrons from the surface states. The amount of electrons emitted from surface states depends on the amplitude and width of filling pulses. The density of 2DEG under ungated surface increases and gradually becomes steady as virtual gate effect weakens. When filling pulse switches to reverse bias, the virtual gate effect becomes stronger again and the surface states restart to capture electrons. The relatively slower capture process gives rise to the decreasing capacitance due to the reduced 2DEG, directly resulting in the formation of hole-like trap signals. The reason for slow capture process is that it need experience three steps: electron injection from gate, electron transport on the surface and electron capture at surface states. During our measurements it is found that the negative signal does not appear when reverse voltage is -2 V and pulse width is 0.1 ms. E1 (Ec-0.88 eV, σ=1.4×10-13 cm-2) and E2 (Ec-0.33 eV, σ=6.1×10-18 cm-2) are detected. The traps are considered in the AlGaN barrier layer under this bias condition. The origin of E1 is supposed to be nitrogen antisites, the same as the trap with energy of Ec-0.56 eV in the interface, because in AlxGa1-xN material the activation energy becomes larger and the signal peak moves towards high temperature direction for congener traps as Al composition increases. E2 is supposed to be nitrogen vacancy which was not detected on account of the influence of surface states when filling pulse width is 0.1ms. As a result of the low reverse bias, the formation of virtual gate is suppressed and the quantity of surface states participating in dynamic process is very small, which has little impact on the detection of electron traps. The DLTS measurements under different bias condition are carried out in this paper. Hole–like traps are detected as a result of surface states emitting and re-capturing electrons. And DLTS signal peak height of the electron traps is reduced and even disappears as the presence of plentiful surface states. Suppression of surface states is very important to not only optimize the performance of device but also improve veracity of electron traps DLTS measurements in AlGaN/GaN heterostructure. In addition, traps on the surface need to be further researched, in order to be controlled better. References [1] Park Y S, Lee M, Jeon K, Yoon I T, Shon Y, Im H, Park C J, Cho H Y and Han M S 2010 Appl. Phys. Lett. 97 112110 [2] Fang Z Q, Look D C, Kim W, Fan Z, Botchkarev A and Morkoç H 1998 Appl. Phys. Lett. 72 2277 [3] Cho H K, Kim C S and Hong C H 2003 J. Appl. Phys. 94 1485 [4] Asghar M, Muret P, Beaumont B and Gibart P 2004 Mater. Sci. Eng. B. 113 248 [5] Fang Z Q, Polenta L, Hemsky J W and Look D C 2000 11th International Semiconducting and Insulating Materials Conference, July 3-7, 2000, Canberra, Australia, p. 35 [6] Tanaka T , Shiojima K, Otoki Y and Tokuda Y 2014 Thin Solid Films 557 207 [7] Sasikumar A, Arehart A, and Ringel S A 2012 IEEE International Reliability Physics Symposium, April 15-19, 2012, Anaheim, California, USA, 2C. 3.1 [8] Duc T T, Pozina G, Son N T, Ohshima T, Janzen E , and Hemmingsson C 2015 Phys. Status Solidi B 1-6 [9] Zhang Z, Farzana E, Sun W Y, Chen J, Zhang E X, Fleetwood D M, Schrimpf R D, McSkimming B, Kyle E C, Speck J S, Arehart A R, and Ringel S A 2015 J. Appl. Phys. 118 155701

Resume : An intensive development of terahertz (THz) science and technology going on for more than two decades have revealed the spectrum of applications in such fields as medical diagnostic, security imaging, broadband telecommunication. Despite a huge experimental efforts, the problem of high output power, compact and electrically tunable THz sources, still exists. The semiconductors are considered as a promising option because the carrier’s plasma oscillations frequency conveniently falls into THz frequency (100 GHz – 10 THz) range. Also in the field effect transistor-like structures the frequency of plasmonic THz emitters can be electrically controlled by tuning the free carrier’s density. Controllable THz emission and detection driven by the plasma oscillations in 2DEG has been demonstrated in plasmonic-devices based on Si and GaAs/AlGaAs heterostructures. However, the observed emission intensity was weak due to a limited input electric power which can be dissipated without damaging the device. Due to a good resistivity to mechanical and thermal stress and high electric fields, the GaN/AlGaN heterostructures are considered as a good candidates for further progress of compact THz emitters. In this work, the resonant THz emission was experimentally investigated employing the 2DEG plasmons in AlGaN/GaN heterostructures grown on sapphire substrate. GaN/AlGaN high electron mobility transistor (HEMT) structures were grown on a sapphire substrate by a conventional Metal Organic Chemical Vapor Deposition (MOCVD) technique. The top surface of the sample was equipped with a metal grating of 2 mm x 2 mm size fabricated between two ohmic contacts. The wave vector of 2D plasmons was quantized by a period of the grating. We used two different grating periods of L1 = 1.0 μm and L2 = 6.9 μm. In latter case, each electrode was formed by a stack of 20 nanoelectrodes positioned with the period of l2 = 200 nm (design of double modulated grating). The THz emission was excited electrically using the source-measure unit (SMU) in pulsed voltage regime with repetition rate of 12.5 Hz. The amplitude and duration of the pulses was varied from 60 V to 100 V, and from 0.8 ms to 2 ms, respectively. The emission spectra at frequencies from 50 cm-1 to 500 cm-1 (1.5-15 THz) were measured using far-infrared Fourier (FTIR) spectrometer at sample temperature of 100 K. The emission signal was collected from the spot of 1.5 mm in diameter using the custom designed optics and experimental setup. At higher frequency range above 300 cm-1, the spectra demonstrated an intense emission arising from the black-body radiation of the sample. While at the red spectrum wing, the resonance THz emission was observed with the peak frequency corresponding to the theoretically calculated fundamental mode of the ungated plasmons. THz plasmonic emission from GaN/AlGaN HEMT structures with two different gratings was experimentaly compared. The results have practical value paving the way towards efficient THz sources based on the plasmonic effects in GaN/AlGaN heterostructures.

Resume : High electron mobility transistors (HEMT) based on the formation of two-dimensional electron gas (2DEG) near the interface between the GaN channel and the AlN barrier, constitute excellent electronic amplifiers at microwave frequencies. For compatibility and safety, it is desirable to develop enhancement-type HEMTs, which do not conduct unless positive bias is applied at the gate. Without additional technological steps such as etching, this “normally-off” operation can be achieved by means of acceptor doping the barrier layer, and subsequent introduction of negative spatial charge that repels electrons and depletes the 2DEG. Heavy p-doping of the top AlGaN layer by Mg(2+), however, can present another technological challenge in the diffusion of the Mg atoms into the channel, which not only reduces doping effect, but also deteriorates the 2DEG mobility. Different experimental sources suggest that significant diffusion can occur at the scale of 20 or even 50 nm, which is of the same order of magnitude as the thickness of the entire barrier layer. I therefore present a comparison of several technologically achievable doping profiles of the barrier layer and compare their impact on the 2DEG density and HEMT threshold voltage.

Resume : We demonstrate that the well-known buffer related ?kink? behaviour in the knee region of the output characteristics of AlGaN/GaN on SiC HEMTs can also have a deleterious effect on pulse IV at high drain bias. Contrary to previous reports, the magnitude of the kink appears to be directly dependent on OFF state gate stress and high ON state drain bias, and is consistent with field accelerated trapping/detrapping giving reduced current. Kink has been believed to be relatively innocuous, since it was thought that the responsible traps were uncharged at high drain bias and hence would not impact RF performance. However, we show that trapping occurs at high drain bias (>20V) in less than a microsecond, even affecting pulse IV measurements from an unbiased quiescent operating point, and resulting in a reduction in output current that will impact RF performance. The inference is that the trap states responsible for the kink are negatively charged deep acceptors. We also demonstrate that kink is not fundamental to the epitaxy: we show results for two wafers with identical processing and layer structure but with different epi growth conditions. Using pulse and transient studies we established that one wafer generated kink with extracted activation energy of 0.43eV and the other had almost no kink and an ideal pulse IV characteristics.

Resume : Introduction Gallium nitride (GaN) based devices are promising as the next generation power devices because of its unique physical properties such as wide band gap, high thermal conductivity, high electron saturation velocity, high physical and chemical stability, and high breakdown field [1]. The formation of ohmic contacts to GaN is essential to minimize power losses. Multilayer contacts are used for GaN, which are based on titanium thin films directly forming the contact to the nitride surface. Process at high temperature after the deposition of multilayer metal are required for realizing low ohmic contact. Such high-temperature processes, however, would cause the dendrite branches of the contact layer surfaces, which could increase the contact resistance and degrade the performance of the devices [2]. Therefore, the ohmic contact material with high temperature stability to GaN is essential. The growth of GaN on Si is possible, which could overcome this problem. Because the value of the work function for Si is close to that of GaN. However, it is difficult to fabricate Si/GaN heterojunctions without buffer layers, because of the large lattice mismatch and difference in thermal expansion coefficients between Si and GaN [3]. In this work, we directly bonded n+-Si substrates to n-GaN epitaxial substrates to fabricate n+-Si/n-GaN heterojunctions using surface activated bonding and investigated their electrical properties. Experimental method (100) n+-Si substrates and n-GaN epitaxial substrates were used for the bonding experiment. The GaN epitaxial layers were grown by metal-organic chemical vapor deposition on (0001) sapphire substrate, consisting of a nucleation layer, a 200 nm undoped GaN layer, and a 2 μm Si-doped n-GaN (3×1018 cm-3) layer. The Hall measurements at room temperature revealed that the resistivity and carrier concentration were 0.002 Ω·cm and (ND =) 2.64 × 1019 cm-3 for the n+-Si substrates, respectively. n+-Si and n-GaN epitaxial substrates were bonded to each other at room temperature by SAB, so that n+-Si/n-GaN heterojunctions were fabricated[4, 5]. The Si substrate of the bonded samples were thinned to the thickness of about 6.5 m by mechanical polishing and chemical etching. And then a 17 μm Al foil was bonded to the polished Si substrates by using SAB. Mesa structures for transmission line measurements (TLMs) were created by wet etching Al foil and dry etching Si with a reactive ion etch (RIE). The fabricated samples were separately annealed at 600, 700 and 800 °C for 60 s in N2 gas ambient. An Agilent B2902A Precision Measurement Unit was used for measuring the I-V measurements of the junctions at room temperature. Results The electrical properties of n+-Si/n-GaN heterojunctions fabricated by surface activated bonding (SAB) were investigated. The current-voltage (I-V) characteristics of n+-Si/n-GaN heterojunctions without annealing showed rectifying property and become excellent linearity property after annealing at 600 °C. The interface resistance was found to be 1.8×10-3 Ω·cm2. Furthermore, the resistance decreased with increasing annealing temperature and decreased to 3.75×10-5 Ω·cm2 after the junctions annealing at 800 °C. These results demonstrate that n+-Si/n-GaN heterojunctions are suitable for the formation of ohmic contacts in the fabrication of GaN-based power devices. REFERENCES: [1] V. Kumar, W. Lu, R. Schwindt, A. Kuliev, G. Simin, J. Yang, M. Asif Khan, and I. Adesida, IEEE Electron Device Lett. 23, 455 (2002). [2] S. Pookpanratana, R. France, R. Félix, R. Wilks, L. Weinhardt, T. Hofmann, L Tati Bismaths, S. Mulcahy, F. Kronast, T. D. Moustakas, M Bär, and C. Heske, J. Phys. D: Appl. Phys. 45, 105401 (2012). [3] S. Lawrence Selvaraj, T. Suzue, and T. Egawa, Appl. Phys. Express 2, 111005 (2009). [4] J. Liang, S. Nishida, T. Hayashi, M. Arai, and N. Shigekawa, Appl. Phys. Lett. 104, 161604 (2014). [5] J. Liang, T. Miyazaki, M. Morimoto, S. Nishida, N. Watanabe, and N. Shigekawa, Appl. Phys. Express 6, 021801 (2013).

Resume : SiO2 is one of the possible materials that can be used for the gate dielectric of GaN-MOSFETs. However, it is known in experiments that a gallium oxide (Ga2Ox) layer is formed at the n-type GaN/SiO2 interface and that Ga2Ox is not formed on the p-type GaN. A mechanism for the formation of Ga2Ox at the n-type GaN/SiO2 interface is proposed in this study. We focus on oxygen vacancy (VO) defects in the SiO2. The formation energy of the VO defect is reported to be about 5.1 eV in the neutral state. When two electrons are trapped by this defect, Si dangling bonds appear and form the defect level about 3.8eV above the SiO2 valence-band maximum, which is about 2.8 eV below the GaN conduction-band minimum [1]. This defect level in the neutral state is unoccupied so that this level traps two electrons. At the n-type GaN/SiO2 interface, the two electrons come from the donor energy level in the GaN (close to the conduction-band minimum in GaN). Then, the energy gained by each electron is about 2.8 eV. This value is larger than the formation energy of the VO defect, which means that the SiO2 emits an O atom and a VO defects arises in the SiO2. Consequently, it is predicted that Ga2Ox appears at the n-type GaN/SiO2 interface as a result of O atoms emitted from the SiO2. On the other hand, in the case of p-type GaN, the energy gain from the electron transfer is so small. Therefore, Ga2Ox is formed only at the n-type GaN/SiO2 interface. [1] X. Shen et al., Appl. Phys. Lett. 106, 143504 (2015).

Resume : GaN based high electron mobility transistors have received a lot of interest for its immense potential various applications. Ohmic contact is an important optical part of the device and various methods have been developed over time to improve it. Still more research is being carried out to improve it further. Here we have demonstrated that various plasma treatments on surface augmented with controlled etching technique can reduce the contact resistance in an optimum way. While it is known that plasma treatment can remove native oxide and there by improve ohmic, however a physical component using Ar improved it further by allowing the metal diffusion during annealing through screw dislocations and reduce the contact resistance by more than 20 %. The TiN alloy can efficiently tunnel inject the carriers due to reduced barrier thickness. We have also verified the improvement with respect to the established surface treatments for ohmic contact formation. We have also made high electron mobility transistors and demonstrate the translation of ohmic contact improvement to device RF characteristics. The proposed mechanism is established through physical characterizations using EDX and TEM.

Resume : AlGaN/GaN based devices have garnered much interest in recent years due to their suitability for high frequency, high power and high temperature applications. In order to convert AlGaN/GaN HFET type devices into normally-off operation, a recess needs to be partially etched into the AlGaN layer (typically 10-20 nm through the layer) to reduce the gate-channel separation. The quality of this surface after etching is of critical importance to the device performance, as any added damage can increase the on-resistance. Low damage etching of AlGaN and GaN substrates were studied using the PlasmaPro100 Cobra300 system from Oxford Instruments Plasma Technology. This system is capable of using ICP-RIE, RIE or Atomic Layer Etch (ALE) plasma etching modes thanks to advanced hardware and software controls. These techniques were used to etch shallow depths of between 5 and 20 nm in both AlGaN and GaN substrates and the resultant etched surface layer quality (Sa) was measured using vertical scanning interferometry (VSI). For ICP-RIE and RIE type processes, it was found that varying gas ratios of Cl2, BCl3 and Ar and bias powers affected the amount of surface damage, but surface roughness still increased slightly as the etch progressed, reaching 0.7 nm added roughness for a 20 nm etch depth. For an ALE type process using Cl2 and Ar, surface roughness was measured to have improved by 0.4 nm for both AlGaN and GaN surfaces. These results highlight ALE as the technique of choice when surface quality is the critical factor.

Resume : Gate-low-damage etching is often used in the fabrication process of GaN HEMT. However, recessed HEMTS will cause larger leakage current through the Schottky gate, which may cause lower broken-down voltage, extra noise and reliability problems?1-2?. the N vacancies induced by plasma in the AlGaN surface is one of the main causes of Schottky leakage?3?. In this paper, theN2 plasma surface treatment of GaN HEMT devices is reported. combined with rapid annealing process, N2-plasma treatment can effectively reduce Schottky's reverse leakage current. The epitaxial layers consists of a 1.5nm GaN cap layer,22nm Al0.25GaN, 2nm AlN and GaN buffer layer. The main process for GaN HEMT devices followed the steps: a)maker; b) ohmic contact ; c) isolation; d) gate etching; e) N2 plasma treatment and anneal; f?gate metallization f)second passivation by PECVD ?f) via and metal. For comparison. Conventional HEMT without N2 plasma treatment is also fabricated simultaneously. After the gate etching, the surface treatment of N2 plasma was carried out by inductively coupled plasma. The source-drain and gate length are 4.0µm and 0.25µm. Fig.1 shows the cross section of AlGaN/GaN HEMT. Current collapse was observed under the pulsed IV measurement, Figure 2 shows the comparison of the device results between different samples. the sample A were only annealed at 400? for 60seconds in nitrogen atmosphere. the Sample B was treated by N2 plasma followed by rapid annealing in nitrogen atmosphere. The two sample GaN HEMTS show roughly the same current collapse (shown in figure2).Compared with untreated samples, the reverse leakage current of the Schottky is reduced by two orders of magnitude. (shown in figure3). Measurements are performed in continuous wave (CW) mode, Fig.4 shows load-pull power measurements of this 4×100?m device at 10 GHz. The device is biased at a voltage of 28V.compared to untreated sample, can supply a peak output power of 3.02W/mm(CW) with63.30% PAE at 10 GHz higher than that of untreated sample. Such a good RF power performance comes from the lower gate leakage by using plasma-induced surface treatment. In conclusion, we present an effective N2 plasma treatment prior to Gate metallization to improve the Ni/GaN interface quality. The N2 plasma can treatment can partially restore nitrogen deficiency and remove surface impurities, which effectively reduces the gate leakage.

Resume : Schottky diodes and FinFETs were pointed out as potential key elements for future RF and terahertz electronics. The design of the lateral Schottky with the contact directly to the side of the electron 2D channel in GaN/AlGaN system provides an advantage of extremely small capacitance and series resistance. GaN-based FinFETs are potential elements of RF and THz generators, amplifiers, mixers, and multipliers. In this work we present experimental results on processing and test of both types of these innovative devices. The Schottky diodes and FinFETs based on high quality GaN/AlGaN heterostructures were grown by molecular beam epitaxy. The current voltage characteristics of Schottky diodes demonstrated small ideality factor of n=1.2-1.25, apparent barrier height b=(0.59-0.63) eV, and high reverse breakdown voltage exceeding 90 V. The FinFETs demonstrated high on to off ratio, close to unity sub-threshold slope, and extremely small gate leakage current. Low frequency noise (LFN) is one of the main limiting parameters of RF and THz devices. The measurements of the LFN in studied devices demonstrated the superposition of 1/f and generation recombination noise. Investigated the noise current squared dependence to the current for lateral GaN/AlGaN Schottky diodes is often found in Schottky diodes based on other semiconductors. The saturation of the noise current dependence which we observed at high currents can be attributed to the influence of the series resistance. In comparison with regular GaN-based Schottky diodes and FETs the devices studied in this work demonstrate the low frequency noise of the same or even smaller amplitude, so GaN/AlGaN lateral Schottky diodes and FinFETs are very promising devices for RF and THz applications

Resume : In this study, we report improvement of the channel mobility of GaN-MOSFETs with recessed gate structures by utilizing the thermal treatment technique. The AlGaN/GaN hetero structure was grown on Si substrate with a 30 nm-thick Al0.20Ga0.80N barrier layer. Recess structures were fabricated by ICP-RIE to the extent that the AlGaN barrier layer was fully removed. Prior to deposition of gate dielectric, the surface thermal treatments under NH3 ambient were performed. The gate dielectric was SiO2 and the gate metal was TiN. Immediately following the fabrication process of the recess, the bottoms of these structures have rough surfaces and step-terrace structures cannot be observed because of the plasma-induced damage. However, clear step-terrace structures are formed by the thermal treatment. The RMS values of the recess surface roughness are decreased from 0.26 nm to 0.14 nm, which is comparable to those of the as-grown epitaxial film. The channel mobility, calculated from drain-current and drain-voltage characteristics, increases as the RMS values of the recess surface roughness decrease. The channel mobility of the device without thermal treatment is 118 cm2/Vs, and that of the device with thermal treatment is 149 cm2/Vs. These results indicate that the thermal treatment under NH3 ambient is effective for reduction of on-state resistance of GaN-MOSFETs. In addition, this thermal treatment can reduce the interface state densities and suppress the threshold voltage instability.

Resume : Substrates patterned with deep grooves have been proposed to simplify the growth and the strain management in GaN on Silicon by taking benefit from the elastic strain release by free edges. Such a solution is well known for light emitting devices. However, few results have been shown for electron devices such as high electron mobility transistors (HEMTs). In the present work, a Si(111) substrate has been patterned with 120 µm wide square mesas separated by 5 µm deep grooves. An Al0.29Ga0.71N/GaN HEMT structure was grown by molecular beam epitaxy with a 2 µm thick Al0.15Ga0.85N buffer on a strain mitigating stack previously developed for GaN or low Al content AlGaN. Surface inspections confirm the absence of cracks and roughness is unchanged compared to planar growth. Interestingly, contrary to planar growth, X-ray diffraction shows that plastic strain relaxation was inhibited within the 150 nm GaN channel grown on top of the Al0.15Ga0.85N buffer. A device process with TiAlNiAu ohmic contacts and NiAu Schottky contacts was applied to evaluate the electrical properties of the grown films. C-V and TLM measurements reveal the presence of a 2DEG with a density of 6.6E12 cm-2 and a sheet resistance around 500 ohms/sq. Round geometry transistors were measured up to 200 V drain bias. Compared to devices previously fabricated on planar structures with Al0.05Ga0.95N buffers, one order of magnitude lower leakage currents were obtained thanks to the larger Al content buffer.

Resume : Despite a lower growth temperature is generally considered as a drawback for achieving high crystal quality, the necessity to reduce the nucleation temperature of AlN on Silicon has permitted molecular beam epitaxy (MBE) to demonstrate high performance devices like high electron mobility transistors (HEMTs). Compared to metal organic vapor phase epitaxy (MOVPE), the control of the interface between the AlN nucleation layer and the substrate is easier and allowed us to obtain low microwave propagation losses (0.37 dB/mm at 40 GHz) and efficient power transistors (Pout up to 3.3 W/mm at 40 GHz). Also, promising results have been obtained with MOVPE HEMT structures regrown on MBE AlN-on-Si templates. More, the purity of the NH3-MBE grown films (Nd-Na<1E15 cm-3 in GaN) we developed is an advantage as it does not necessitate any compensation doping for resistive buffer layers. As an example, a 2.3 µm thick HEMT structure grown on Silicon with a GaN buffer exhibits a vertical breakdown voltage larger than 400 V while it reaches more than 700 V within a 2 µm structure with an Al0.05Ga0.95N buffer. Besides, lowering the temperature limits the parasitic diffusion of implanted impurities in Silicon CMOS devices and permits to control the drift of the electrical properties of the latter. As a consequence, the recent optimizations we made leading to growth temperatures below 850 °C for AlN constitute a promising way for the monolithic integration of GaN HEMTs with Silicon MOS technology.

Resume : A lot of research has been carried out to increase the threshold voltage of HEMT devices toward enhancement-mode (E-mode) operation in order to reduce circuit design complexity, include device failsafe, or even realize digital integrated circuits. A number of techniques, including gate recess, p-type III-nitride gate, fluorine plasma ion implantation, and gate-controlled tunnel junction have been proposed and demonstrated to realize normally-OFF operation based on GaN-based heterojunctions. Although promising results have been achieved by these ways, they have the disadvantages of damaged barrier layer, poor gate-electrode control ability and poor thermally stable. A recess-free thin barrier device structure would be preferable to prevent the potential damage caused by the recess on the channel, to reduce technical difficulties in terms of uniformity and reproducibility and to improve the gate-electrode control ability. In this paper, we present an enhancement-mode ultrathin AlN barrier HEMT which control the Vth by slight surface oxidation treatment to reduce and atomic-layer-deposited (ALD) Al2O3 dielectric to increase the 2DEG density, respectively. The E-mode AlN barrier HEMT shows a positive Vth, a high maximum drain current (IDmax) of 970 mA/mm, a low off-current (Ioff) of 2.6×10^-4 mA/mm, a low on-resistance of 3.2 Ω·mm, a large Ion/Ioff of 10^7, a low gate leakage current of 3.4×10^-4 mA/mm and low subthreshold swing (SS) of 70 mV/dec. The HEMT structure that consisted of, from bottom to top, a 2.0-nm GaN-cap layer, a 3.0-nm AlN barrier, a 1.2-μm undope GaN channel, and a 200-nm AlN nucleation layer was grown on a sapphire substrate by metal-organic chemical vapor deposition (MOCVD). 4nm-ALD-Al2O3 dielectric was deposited to increase the 2DEG at the gate-source and gate-drain regions and improve the IDmax. The Al2O3 dielectric at the source, drain and gate regions was removed by buffered oxide etch. By a slight surface oxidation treatment, an ultra-thin native oxidation layer formed on the GaN-cap surface and causes the reduction of 2DEG density. The GaN-cap effectively protected the AlN barrier layer without oxidation, which was proved by XPS measurement. This is different with the reported result about positively shift of threshold voltage result from the decreasing of AlN layer thickness by oxidizing the AlN into Al oxide. Un-oxidized AlN barrier layer is important to ensure the recovery of 2DEG density by ALD-Al2O3 dielectric. Room-temperature (RT) Hall measurement presents the HEMT layer shows a sheet resistance of 677 Ω /sq, a sheet electron density of 0.7×10^13 cm^-2, and a high Hall mobility of 1626 cm^2/V.s. The sheet resistances of sample depended on the surface oxidation treatment time. After surface oxidation treatment, the samples were deposited Al2O3 (4 nm) dielectric to recovery and increase 2DEG density. After depositing Al2O3, the oxidation treated sample with sheet resistance of 4666Ω /sq presents a sheet resistance of 415 Ω/sq and a Hall mobility of 1514 cm^2/V.s. For the device characteristic, the HEMT with sheet resistance of 4666 Ω/sq after surface oxidation treatment were normally off, with a Vth of 0.20 V by linear extrapolation. The Vth could be improved by increasing oxidation treatment time. It also shows a large Ion/Ioff of 10^7, low SS of 70 mV/dec, a maximum transconductance of 360 mS/mm, a large IDmax of 970 mA/mm at Vds of 6 V, the quit low drain current of 2.6×10^-4 mA/mm and gate leakage current of 3.4×10^-4 mA/mm at Vgs = -8 V. Moreover, by re-depositing ALD-Al2O3 gate dielectric (7 nm) and without surface oxidation treatment, we also achieved D-mode MIS-HEMT, D-mode HEMT devices on the same wafer. The MIS-HEMT with 7 nm Al2O3 gate dielectric shows a Vth of -4.6 V, IDmax of > 1A/mm, a large Ion/Ioff of 10^10 (Ioff of 3.6×10^-7 mA/mm at Vgs=-10V) and a low SS of 68 mV/dec.

Resume : To investigate plane orientation dependence of material properties we are developing m-plane Gallium Nitride (GaN) power devices. It is already reported that m-plane epitaxial layer has pyramidal hillocks [1]. Schottky barrier diodes (SBD) on the facet inclined toward [0001] have leakage current [2]. To reveal characteristic of four facets forming pyramidal hillocks, we investigated off angle dependence of m-plane SBD characteristics. Commercially available n-type GaN (10-10) substrates with several off-cut angles of 5° toward the [0001] (+c5°), 5° toward the [000-1] (-c5°), and 0.5° toward the [-12-10] (a0.5°) were used for single facet epitaxy [3]. Undoped GaN layer was grown on the substrates by metalorganic vapor phase epitaxy (MOVPE). Then Ti/Al/Ti/Au ohmic electrode and Ni/Au Schottky contacts were fabricated. Sample +c5° shows SBD characteristics. And the others have quite low current on both backward and forward biased conditions (less than 1e-5 [A/cm^2] @-100V and @+5V). Then we observed epitaxial layers with Secondary Ion Mass Spectrometry (SIMS). Impurities with highest concentration in each epitaxial layer are as follows. Sample +c5° has oxygen with order of 1e17 [Atoms/cm^3]. Sample -c5° has oxygen with order of 1e15 [Atoms/cm^3]. Sample a0.5° has carbon with order of 1e16 [Atoms/cm^3]. We revealed that the difference of those impurity concentration of epitaxial layers on each off-angled substrate causes the difference of device characteristics. Acknowledgement This work is supported by the Cross-ministerial Strategic Innovation Promotion Program (SIP). [1] C. Q. Chen et al., Appl. Phys. Lett., 81, 3194 (2002) [2] A. Tanaka et al., IWN2016 PS2. 162 (2016) [3] A. Hirai et al., Appl. Phys. Lett., 91, 191906 (2007)

Resume : Gallium nitride (GaN) is a promising candidate for high-power and high-frequency devices. However, to date the lack of large area cheap bulk GaN materials has limited the technology almost completely to lateral devices architectures. Now, with the improvement of bulk GaN technology, vertical structures are attracting more interest, as they enable to obtain a higher current density and a reduced device size, also avoiding detrimental surface-effects, which typically affect the lateral devices. In this work, the electrical behavior of Ni Schottky contacts on commercial bulk GaN material was studied. Vertical Schottky diodes have been fabricated on 3 μm thick n-type GaN epitaxial layer (1x10^16 cm-3) grown onto heavily doped (1-5x10^18 cm-3) GaN substrates, using an annealed Ti/Al/Ni/Au Ohmic back contact. The forward current-voltage (I-V) characteristics revealed a temperature dependence of both the ideality factor and of the Schottky barrier height. The correlation between the ideality factor and the Schottky barrier height indicated the occurrence of an inhomogeneous barrier. The value of the barrier extrapolated at n=1 was 1.7eV, in agreement with the results obtained by capacitance-voltage (C-V) measurements. A nanoscale electrical analysis performed by conductive atomic force microscopy (C-AFM) allowed to visualize the local distribution of the barrier height values. The full width at half maximum of this distribution described the degree of barrier inhomogeneity and allowed to explain the temperature behaviour of the macroscopic diodes.

Resume : GaN-based metal-insulator-semiconductor (MIS-) fully recessed gate field-effect-transistor (FET) and partially recessed high-electron-mobility transistor (HEMT) are two attractive power devices for the suppression of leakage current, large gate swing as well as enhancement-mode (E-mode) operation [1]. A comparative study of MIS-HEMTs and MIS-FETs is of particular interest. In this work, the static performance, thermal stability as well as reliability of E-mode MIS-HEMTs and MIS-FETs with the same gate dielectric stack are compared in details. The studied MIS-HEMTs and MIS-FETs were fabricated with identical process flow as the same as those reported in ref. [2], except that the MIS-FETs feature a fully recessed gate, while the MIS-HEMTs have a ~2.6 nm thin AlGaN/AlN barrier layer remaining between the gate dielectric and channel. The gate dielectric stack process consists of a ~2 nm PECVD-SiNx prepared at 300 °C followed by an LPCVD-SiNx layer deposited at 780 °C [3]. Both MIS-HEMTs and MIS-FETs deliver positive VTH of 0.4 V and 2.37 V, as well as small VTH hysteresis and subthreshold swing (SS), benefiting from the high-quality III-N interface. The MIS-FETs do suffer from lower channel mobility (~160 cm2/Vs) that results in larger RON (13 ohm/mm) because of the removal of the heterojunction channel. The thermally stable VTH of MIS-FET is significantly better than that of the MIS-HEMTs, showing a smaller shift of -0.21 V compared to a -0.76 V shift in the MIS-HEMTs, from 25 °C to 200 °C. As the VTH thermal instability originates from the thermal-assisted de-trapping from the deep traps between EC and EF at the dielectric/III-N interface, narrower ?E=EC-EF in MIS-FET suggests that deep interface traps cannot participate in the thermal emission, contributing to the enhanced VTH thermal stability [4]. Gate stability tests were conducted at both 25 °C and 150 °C for 10,000 s with the stress conditions set at VGS = 10 V for PBTI and VGS = -30 V NBTI measurement, respectively. A small shift of < 0.2 V is observed at room temperature at both BTI stress conditions. At elevated temperature (150 °C), slightly larger VTH shift of 0.64 V and 0.9 V were measured in MIS-HEMTs and MIS-FETs in PBTI test. As for NBTI at 150 °C, MIS-HEMTs and MIS-FETs show VTH shift of 0.6 V and 0.4 V. Non-negligible SS degradation (a 15% increase from 105 mV/dec to 121 mV/dec) was observed in MIS-HEMT at 150 °C while MIS-FET remains stable after negative gate bias stress, indicating possible degradation (due to generation of new defects) of the thin barrier layer under long-term electrical stress. REFERENCES: [1] T. Oka, et al., IEEE Electron Device Lett., Vol. 29, no. 7, p. 668?670, 2008. [2] M. Hua, et al., IEEE EDL, Vol. 36, p. 448, 2015. [3] M. Hua, et al., IEDM 2016. [4] S. Yang, et al., IEDM 2014, p. 434.

Resume : GaN-on-silicon substrate offers a cost effective technology for a large-scale deployment of high electron mobility transistors (HEMTs) for power electronic applications. As the silicon substrate now playing a major role for GaN epitaxial growth, an obvious trend of research focuses to develop silicon compatible front-end processes to make further reduction of device cost. The traditional devices of such high performance nitride systems have been dominated by Au-based contacts. From device cost versus performance point of view, metal contact processes are not limited only to high voltage applications but also RF and light emitting diode applications of such nitride systems. In this context, there is a need for a CMOS compatible process technology, which can be applicable for fabrication of GaN transistors on large area Si substrates. In our studies, we have demonstrated fabrication of HEMTs on Si(111) platforms with Au-free source/drain and gates. The AlGaN/GaN HEMT epilayers on Si(111) are grown by a metal organic chemical vapor deposition process. The HEMT top active layers, comprising of 1.0-1.5 nm AlN spacer, about 20 nm undoped AlxGa1-xN barrier (Al: 23%), and undoped 2-3 nm thin GaN cap, on GaN buffers are used to develop Au-free Ohmic contacts. Series of Ti/Al-based Ohmic contact metal stacks are used (thermal anneal temperature window of 450 – 850 oC) to benchmark contact resistance on these 2DEG layers without any recess etching for source/drain. Among various metal stacks, Ti/Al/Ni/W and Ti/Al/NiV layers led to contact resistance (RC) <0.8 ohm.mm without source/drain recess. Furthermore, insertion of a thin Ge layer (<10 nm) beneath Ti/Al-based layers led to a dramatic decrease in the RC < 0.3 ohm.mm which is quite similar to the case of Ti/Al/Ni/Au-based contacts on such HEMT structures grown on Si substrates. The improved Ohmic contact property is found out to be due to the diffusion of Ge on the thin GaN cap and formation of thin metal-germanide interfaces. Furthermore, we have also demonstrated Au-free InAlN/GaN high electron mobility transistor (HEMT) structures on Si (111) substrates. The crystalline quality of the InxAl1-xN barrier layers in HEMT stack is affected in traditional high temperature Au-based contact processes and thus, the gate leakage dominates the DC characteristics. To minimize the InxAl1-xN surface morphological defects in such contact processing steps, we have also shown Au-free route using Ti/Al/NiV-based Ohmic source/drain contacts. With low-temperature annealing at 500 oC for source/drain contacts and 2.0 μm Schottky gate, InAlN/GaN-HEMTs fabricated on Si exhibited maximum transconductance (gm) and saturation drain current (IDSAT) of ~180 mS/mm and ~980 mA/mm, respectively. The impact of such processes on HEMT characteristics in both AlGaN- and InAlN-type barriers layers with different sets of Au-free gate metals will be discussed.

Resume : Due to its wide bandgap, chemical stability, and availability of aluminium (Al)GaN/GaN heterostructures, there is strong interest in the development of GaN based high-power, high-temperature electronic devices, such as AlGaN/GaN high electron mobility transistors (HEMTs). Because the same reason, it is very difficult to develop wet chemical etchants based on conventional acids and alkalis. In this paper, the BCl3/Cl2 and BCl3/Cl2/Ar-based etch recipes of ICP etching process were studied. The etched surface roughness, respectively, Rq=1.829nm and 0.762nm, were obtained. In the etching process, BCl3/Cl2 and BCl3/Cl2/Ar etch recipes were applied in different regions respectively in the same wafer. After etching process, the gate metal deposition process carried out. It can be seen from the characteristics of the Schottky of GaN/AlGaN HEMT device, using BCl3/Cl2/Ar etch recipe etched region, the Schottky reverse leakage current is significantly reduced almost two orders of magnitude. The gate recess was etched by BCl3/Cl2/Ar and BCl3/Cl2, and Vth=-2.5v and Vth=-3.6v respectively. The shift of the Vth to the positive direction shows that the control ability of the gate was enhanced. It proves that a good AlGaN surface topography under the gate metal can improve the performance of the device.

Resume : Owing to the presence of the two-dimensional electron gas (2DEG) and to the high electric field strength of GaN-based materials, AlGaN/GaN heterostructures are excellent systems for high-power and high-frequency HEMTs. Clearly, for power electronics applications, normally-off switches are preferred. The use of a p-GaN gate is one of the most promising approaches to achieve normally-off HEMTs. In this context, studying the behavior of metal gate contacts is very important, due to the possible impact of the electrical parameters of the device (leakage, threshold voltage, etc.). In this work, the current transport properties metal/p GaN interfaces have been investigated using different metal stacks (Ti/Al, TiN/Ti/Al, Ni/Au, W). For this purpose back-to-back” Schottky contacts have been fabricated onto p-type GaN layers, with a holes concentration of 2x10^17 cm-2. To get insights on the transport properties at the Schottky interfaces, temperature dependence of the current-voltage (I-V) characteristics has been studied for these systems. The Thermoionic Field Emission (TFE) was found to be the dominant transport mechanism, allowing to determine the metal/p-GaN Schottky barrier height values FB. Clearly, different values of FB were found depending on the metal work function and on the processing conditions. The electrical behavior of the metal/p-GaN interfaces has been monitored also after thermal treatment both on p-GaN and on AlGaN, thus giving useful information for the integration of such systems either as Schottky or Ohmic contacts in normally-off HEMT technology.

Resume : An attempt was made to modify the Schottky barrier height, ΦB, at the metal/GaN interface by inserting ultrathin Al2O3 interlayers. A Si-doped n-type GaN epitaxial layer with the doping density of 5×10^16 cm^-3 was grown onto a free standing GaN substrate. For the samples with interlayers, ultrathin Al2O3 layers of 1 nm thickness were deposited by atomic layer deposition (ALD). As the metal layers, Ag, Cu, Au, Ni, and Pt were deposited by the electron beam evaporation. Samples without interlayers were also fabricated for comparison. For the Ag/GaN interface, the insertion of ultrathin ALD Al2O3 interlayer lead to an increase of ΦB of 330 meV. The Cu/GaN interface with the interlayer also showed an increase of ΦB of 160 meV compared with the sample without the interlayer. However, the Ni/GaN sample exhibited a decrease of ΦB of 120 meV by insertion of the interlayer. Smaller changes of ΦB were measured for Au/GaN and Pt/GaN interfaces. In a plot of the measured ΦB vs. the metal work function, ΦM, the samples without interlayers indicated a fair dependence of ΦB on ΦM with dΦB /dΦM = 0.25, while the sample with the interlayers were characterized with strong pinning of ΦB at 0.9 eV. The mechanism for the enhancement of Fermi level pinning by insertion of the ultrathin Al2O3 interlayers will be discussed.

Resume : Present study of GaN HEMT for power electronics is foucused on HEMT on Si. However, the technology for producing GaN bulk substrates inexpensively has been proposed and studied recently. Because GaN bulk substrate can become semi-insulating, high-speed response by reduction of drain-source capacitance can be expected by GaN HEMT on SI-GaN substrate. Such superior characteristics has possibility to reduce loss even at a high frequency which has never existed before.Moreover, as all terminals of GaN HEMT are located at top-side,the possibility that monolithic integration of power devices is also provided. As as an application example of such integrated circuits, a multilevel inverter is one of the candidates. It provides reduction of drain-source capacitance, results in reduction of loss even at high speed. Moreover, required applied voltage to the each devices can be reduced by multilevel configuration.

Resume : Material properties make III-Nitrides an attractive platform for power electronics applications.III-Nitride devices are traditionally fabricated on the Ga-polar (0001) orientation.Due to its inverted polarity, HEMTs fabricated on N-polar (000-1) substrates possess numerous advantages over their Ga-face counterparts[1],as demonstrated by record mm-wave performance[2,3].In addition,N-polar power devices with breakdown voltages over 500 V and low on-resistance (Ron) of 0.89 mΩ.cm2 have recently been reported[4].This work investigates the dynamic Ron performance of N-Polar GaN HEMTs with multiple field plates(FP). N-Polar GaN HEMTs were fabricated on MOCVD epi-layers grown on miscut sapphire substrates.Three FPs were designed for high voltage operation and dispersion management with a slanted,gate-terminated FP[5] and two source-terminated FPs.The devices have a drain current density of ~650 mA/mm at VGS=1 V, and a specific Ron (active area) of 1.55 mΩ.cm2 (7.75 Ω.mm) for Lgd=8 um.DC Breakdown voltage ranged from 650 V to 1475 V for Lgd=8 um to 28 um.The dynamic Ron was characterized by measuring the Ron 1 µs after the device was switched from the off-state to on-state, and was ~2 times the static Ron at 200 V. The authors thank Transphorm Inc. for the dynamic Ron measurements. [1]M.H.Wong et al. Semicond. Sci. Technol. 28(2013)074009(22pp) [2]B. Romanczyk et al. IEDM 2016 [3]S. Wienecke et al. DRC 2016 [4]O. Koksaldi et al. IWN 2016 [5]S. Kolluri et al. IEEE EDL, VOL.33, NO.1, Jan 2012

Resume : GaN high-electron-mobility transistors (HEMTs) on silicon substrate are promising candidates for high power electronics applications owing to their superior intrinsic properties and potential low cost. However, the maximum breakdown of GaN-on-Si HEMTs is limited by the Si substrate mainly due to its poor critical electrical field strength. Several methods to improve the breakdown voltage have been reported, including thicker buffer layers, and local Si substrate removal (LSR). For instance, our group has recently reported state-of-the-art GaN-on-Si HEMTs with three-terminal lateral breakdown voltage over 3 kV by applying the LSR technique [1]. However, in discrete devices or in monolithic integrated circuits as well as for thermal dissipation enhancement (metal heat sink), a grounded substrate is generally used. It can be pointed out that the LSR approach is not useful if the substrate is grounded because the buffer layers need to be isolated from the ground with a high breakdown field material. That is why, the highest reported vertical breakdown VVBR values for GaN-on-Si HEMTs are still below 1.5 kV, which is basically limited by the total buffer thickness and associated material quality [2]. In this paper, we report for the first time substrate grounded GaN-on-Si HEMTs with record vertical breakdown of 2.2 kV after removal of Si substrate and backside deposition of a thick AlN film. The AlGaN/GaN/AlGaN double heterostructures, grown by MOCVD deposition on a Si(111) substrate, consisted of transition layers and a 2 µm Al0.08Ga0.92N buffer layer, followed by a 150 nm GaN channel, 20 nm Al0.25 Ga0.75N barrier layer and a 50 nm in situ Si3N4 cap layer. Ohmic contact pads from TLM structures were formed on AlGaN barrier by alloying Ti/Al/Ni/Au stack using an 875°C rapid thermal annealing. Device isolation was achieved by N2 implantation. On the backside, the Si substrate was locally etched up to the AlN nucleation layer around the entire device. Then, 15 µm thick AlN delivering high breakdown field (> 4MV/cm) was deposited on the backside by Pulsed Vapor Deposition (PVD). Substrate grounded VVBR measurements were performed on the TLMs with and without LSR. The use of LSR and thick AlN dielectric layer enabled a remarkable increase of the VVBR from 720 V to 2.2 kV, confirming the suppression of the substrate conduction phenomena and the effectiveness of the dielectric. This result paves the way for higher voltage operation of substrate grounded GaN-on-Si power devices. [1] Herbecq N, Roch-Jeune I, Linge A, Grimbert B, Zegaoui M and Medjdoub F 2015 Electron. Lett.51 1532 [2] Freedsman J. J., Watanabe A., Yamaoka Y., Kubo T. and Egawa T. 2016 Phys. Status Solidi A 213 424

Resume : GaN-based 2DEG heterostructure field-effect transistors (HFETs) have been highly considered as a candidate device for next-generation high-power/high-speed electronic devices. In addition to conventional AlGaN/GaN heterostructures, ternary AlGaN-channel heterostructures have recently attracted considerable interest owing to their superior properties such as extremely high breakdown fields [1] and low temperature dependence in DC and RF operation [2]. On the other hand, 2DEG heterostructures employing InAlN barrier layers in place of AlGaN barrier layers have also attracted considerable attention. This is because high 2DEG densities of over 2.5e + 13/cm^2 can be achieved without the generation of a high lattice strain owing to the large spontaneous polarization of InAlN [3]. This feature seems to be appropriate for high-drain-current operations. Based on the above, it seems natural to consider lattice-matched InAlN/AlGaN 2DEG heterostructures as candidates for future high-power electronic devices. However, there were no reports on InAlN/AlGaN 2DEG heterostructures until we reported. In this paper, we present our recent results and future prospect of nearly lattice-matched InAlN/AlGaN HFETs. InAlN/AlGaN heterostructures were grown by a horizontal MOCVD system with conventional precursors. Epitaxial AlN/sapphire templates, which consisted of a 1-μm-thick epitaxial AlN film on a 2-inch-diameter c-face sapphire substrate, were used as underlying substrates. The sample structure consisted of the following layers from the bottom to the top: a 2-µm-thick AlGaN channel layer, a 1-nm-thick AlN interlayer, and a 10-nm-thick InAlN barrier layer. Here, the AlGaN channel layer were grown to have the AlN molar fractions of 0.10, 0.21, and 0.34, and the composition of InAlN barrier layer was chosen to be nearly lattice-matched to the AlGaN channel layer. In the result, the 2DEG densities were measured to be higher than 2.5e + 13/cm^2 for all the MOCVD-grown samples. This results confirmed a large polarization effect occurred at the InAlN barrier layers. Although the 2DEG mobility was as low as less than 170 cm^2/Vs at an initial stage of this study, it has been improved up to approximately 250 cm^2/Vs by realizing an atomically smooth heterointerface. This value is fairly close to the theoretical limit of AlGaN-channel heterostructures determined mainly by alloy disorder scattering. As a result, the sheet resistance of the InAlN/AlGaN heterostructures has been reduced up to less than 1000 Ω/sq, which is not so bad compared to conventional AlGaN/GaN heterostructures. A Schottky-gate HFET was fabricated on an InAlN/Al0.21Ga0.79N heterostructure using a conventional photolithographic method. The source and drain patterns were formed by the evaporation of Ti/Al (15/60 nm), which were subsequently annealed at a temperature of 550°C for 30 s in a nitrogen atmosphere. The gate Schottky contact was formed by the evaporation of Pd/Ti/Au (40/20/60 nm). The device dimensions were as follows: source-to-gate distance Lsd = 3 μm, gate length Lg = 2 μm, gate-to-drain distance Lgd = 4 μm, and gate width Wg = 15 μm. The fabricated device showed a good pinch-off characteristic with a high off-state breakdown field of approximately 120 V/μm, which was several times higher than that of conventional GaN-channel HFETs. On the other hand, the drain current density was measured to be as low as approximately 80mA/mm due to their very high ohmic contact resistance. In our experiment, it was shown that the contact resistance occupies the most part of the total device resistance. Also, a simple device calculation based on the experimental results indicated the possibility that the specific on-resistance, RonA, might become considerably lower than that of conventional AlGaN/GaN HFETs by reducing the specific contact resistance up to a value less than 1e - 5 Ω cm^2. Thus, we recognized that a large reduction in contact resistance is indispensable and the great issue to be solved for achieving high-drain-current/ low-on-resistance InAlN/AlGaN HFETs. In conclusion, a nearly lattice-matched InAlN/AlGaN 2DEG heterostructures were grown by MOCVD, which showed an extremely high 2DEG density of over 2.5e + 13/cm^2. It has been confirmed that the 2DEG mobility was improved up to a value close to their theoretical limit by realizing an atomically smooth heterointerface. The fabricated HFET showed a good pinch-off characteristic with a drain current density of approximately 80 mA/mm and a breakdown field of approximately 120 V/μm. A simple device calculation indicated that a lower RonA can be accomplished by reducing the specific contact resistance up to a value less than 1e - 5 Ω cm^2. This work was partially supported by the Super Cluster Program of the Japan Science and Technology Agency (JST), and JSPS KAKENHI Grant Number JP16K06298. [1] T. Nanjo et al., Appl. Phys. Express, 1, 011101 (2008). [2] M. Hatano et al., IEICE Trans. Electron., E95-C, 1332 (2012). [3] J. Kuzmik, IEEE Electron Device Lett., 22, 510 (2001).

Resume : One of the major problems with monolithic integration of GaN power systems based on GaN-on-Si technology is the body effect because all devices are sharing the same Si substrate at a common bias. In this work, we explored a potential solution by combining epitaxial growth using MOCVD on a 200 mm Silicon-On-Insulator (SOI) substrate and deep trench isolation formed in the device fabrication process, such that each individual device is completely electrically isolated from the rest of the devices on the same wafer. We found that the epitaxial growth on SOI substrates behaved very differently from the growth on regular Si substrate. The SOI wafer deformed much more strongly upon the lattice mismatch introduced stress. Hence, delicate strain engineering was required for wafer bow control. Further in-depth study pointed out that the phenomena is associated with the strain partition effect. The fabricated p-GaN enhancement mode high electron mobility transistors were fully functional with a threshold voltage of ~ 1.6 V and qualified for 200 V switching applications at a temperature up to 150 ℃. Moreover, we demonstrated that the electric isolation between devices was very effective such that no deviation of the transistor characteristics was observed when the Si substrate of adjacent devices was biased within -200 V and 200 V range. These results show that our approach is very promising to achieve the complete monolithic integration of GaN power system on a single chip.

Resume : In contrast to most conventional power technologies, such as Power-MOSFETs or IGBTs, the lateral GaN heterojunction technology allows the integration of several components side-by-side on a single chip. Thus monolithic integration of power circuits improves functionality, as well as the performance due to lower parasitics, and reduces the effort for assembly technologies. Here, we present essential strategies in epitaxial growth, design and device processing for the realization of monolithically integrated GaN half-bridges. High quality (Al,Ga)N-based epilayers with both high vertical isolation as well as low trap density are grown using MOCVD on Si(111)-substrates. The layout of the integrated half-bridges consists of two transistors and two freewheeling Schottky-diodes in an area-efficient and low-impedance design with optimized field-plate design (gate and source-connected). Processing is carried out using a tailored surface passivation providing low-leakage (< 1 µA/mm) and high-breakdown (> 600 V) transistors and diodes with minimum static (RON×A < 4 m?×cm²) and dynamic (forward: RON×QG < 1 ?×nC, reverse: RRVS×QRR = 1.8 ?×nC) switching losses. Stable switching operation of the monolithically integrated device (4×4 mm² size) is presented in a DC-DC buck converter for input voltages up to 400 V and switching frequencies up to 3 MHz with output power up to 250 W. Challenges associated with a common device substrate will be addressed. This work demonstrates suitability of a monolithically integrated high voltage half-bridge chip with integrated freewheeling diodes for use in high frequency, soft-switching and resonant switching power converter applications.

Resume : Lateral GaN transistors are widely used today in state-of-the-art RF amplifiers and power electronics. However, in spite of the excellent results shown by these devices and their successful market penetration, their performance is still far from the theoretical maximum for GaN. The relatively low linearity, poor reproducibility of sub-100 nm gate length technology, and the high cost and difficulty of current ohmic regrowth technologies are important challenges of today’s lateral GaN RF devices. At the same time, the reliability, low current density and high device cost limits the penetration of GaN transistors in power electronics above 1000 V. This talk will describe how vertical GaN transistors could help overcome most of the challenges identified above for lateral GaN devices. For example, GaN vertical-fin FETs offer excellent performance as power switches with unprecedented current-density levels. When these transistors are fabricated on Si substrates, the cost is lower than in lateral devices and the performance is significantly improved. In addition, p-type ion implantation can be used to engineer the electric field, reduce leakage current and increase the breakdown. Approaches to scale-down these devices to sub-20 nm gate lengths, including hybrid Graphene/GaN hot electron transistor structures, will also be discussed, which open the door for vertical GaN to be used on advanced digital and mixed signal applications. Acknowledgements.- This work has been partially supported by the ONR PECASE program, monitored by Dr. Paul Maki, and by the ARPA-E Switches program, monitored by Dr. Timothy Heidel and Dr. Isik Kizilyalli.

Resume : This presentation will discuss recent work on new III-Nitride based lateral and vertical device concepts to go beyond the limitations of conventional AlGaN/GaN high electron mobility transistors (HEMTs). We will discuss two methods to realize vertical III-Nitride devices for high frequency electronics. In the first part of the presentation, we will discuss the design and demonstration of ballistic transistors based on hot electron transport. In these tunneling hot electron transistors (or THETA), we have used polarization engineering to overcome leakage and realize high current gain above 10 [1]. In the second part of the talk, we will discuss our work on realizing heterogeneous bipolar transistors that can take advantage of a conductive 2D layered semiconductor base while also maintaining the advantage of a wide band gap GaN collector. CVD and MBE growth techniques to realize heterojunctions between 2D layered semiconductors such as MoS2 and GaSe and GaN [2] will be discussed. Finally, will describe the electrical characteristics of 2-terminal 2D/3D heterojunction devices, and describe our work on realizing 3-terminal transistor structures. [1] Yang, Zhichao, et al. "Current gain above 10 in sub-10 nm base III-Nitride tunneling hot electron transistors with GaN/AlN emitter." Applied Physics Letters 108.19 (2016): 192101. [2] Lee, Edwin W., et al. "Layer-transferred MoS2/GaN PN diodes." Applied Physics Letters 107.10 (2015): 103505.

Resume : Degradation of electric performance with GaN HEMT devices is often caused by plasma-damage during dry-etch process which induces surface roughening, nitrogen missing, and contamination on AlGaN layer. Thus, removal of the damaged-layer is crucial to HEMT devices. In this paper, we report effects of wet-etch process using various chemical solutions on plasma-damaged AlGaN film, and propose the best chemical formulation. A 30 nm-thick AlGaN film deposited on GaN layer was etched off to 15 nm using BCl3/Cl2 gas chemistry. Three chemical solutions selected by combinatorial method; (i) acid, (ii) oxidizer added acid, and (iii) alkaline followed by acid post-treatment, were used for removal of the plasma-damaged layer. A MIS-capacitor TEG was fabricated on the films, and each film surface was evaluated by XPS and AFM. The C-V results showed that variation of interfacial traps depending on each condition. The Vth of wet-etched samples showed negative shift (-5.1~-5.6V) compared to “as dry-etched” (-4.7V), indicating that the wet chemicals successfully removed charge traps induced by dry-etch. The solution (iii) showed the largest shift to Vth=-5.6V, and its dC/dV was twice as high as that of “as dry-etched”. These C-V results shows good agreement with simulated trap model, and also are consistent to the XPS and AFM data. The XPS results showed that O/Ga ratio increased from 0.32 to 1.00 by dry-etch, but after wet-etch it returned to less than 0.31. Moreover, the increase of surface roughness by wet-etch was suppressed less than 0.09 nm.

Resume : In-plane-gate field effect transistors (IPGFETs) offer an innovative architecture in which the channel and gates lie on the same plane of the 2DEG. Gate control is achieved by electric field propagating in the gate 2DEG, which is isolated from the channel by a nanoscale trench. This yields a huge reduction in gate capacitances, down to few aF, promising for high frequency applications. IPGFETs in the literature are mostly based on narrow-gap III-Vs, which offer limited output power due to their low carrier density and low breakdown field. In this work we demonstrate for the first time IPGFETs on AlGaN/GaN. Their fabrication is very simple, relying on one step to isolate the gate from the channel by a nanoscale trench and a common ohmic metallization for gates, source and drain, which allows a self-aligned process. Different device geometries were investigated to optimize drain current (Id) and transconductance (gm). Three different channel lengths (80, 250 and 500 nm) were explored, with channel width ranging from 40 nm to 100 nm, along with two main gate geometries based on trapezoidal and triangular shapes. The simulated gate capacitance was only 8 aF for the smallest device (equivalent to 160 aF/µm). Large Id and flat gm were observed, up to 900 mA/mm and 340 mS/mm, which are 3x- and 2x-larger than the best IPGFETs in the literature, respectively. The threshold voltage reduced from -5 V to -1 V for shorter and narrower devices. The subthreshold slope was largely reduced for medium and short devices, reaching values around 58 mV/dec. For all devices, the Ion/Ioff ratio was up to 1E6 while the gate leakage current was smaller than 100 pA. This first demonstration of GaN IPGFETs reveals the huge prospects of III-nitrides for new device concepts with ultra-small gate capacitances for future high frequency applications.

Resume : The integration of single crystal epitaxial thin metals and superconductors with nitride semiconductors opens possibilities for novel device applications. We present measurements of the superconducting and normal state properties of epitaxial metallic ?-Nb2N films and AlN/Nb2N heterojunctions grown by plasma assisted molecular beam epitaxy on (0001)-oriented Si-face 6H-SiC with Niobium supplied by an e-beam source. Nb2N is near lattice and symmetry matched to SiC. XRD confirmed the phase and epitaxial nature of the Nb2N films. Transport and vibrating sample magnetometry measurements establish the transition of Nb2N to the superconducting state at temperatures between 8K-13.5K for samples of different thickness and growth parameters. Resistivity and Hall effect measurements determined normal state carrier concentration of approximately 2x1023cm-3 and carrier mobility of approximately 1cm2 V-1 s-1. The upper critical field HC2 for samples with different thickness was measured as a function of temperature and the film/field angle, with in-plane HC 2(T=0) determined to be more than 40T in 4nm film, indicating two-dimensional superconductivity. Transmission electron microscopy imaging of the AlN/Nb2N heterojunctions confirms the epitaxial nature of the Nb2N and AlN layers. Finally we present integration of such thin superconducting Nb2N with AlGaN/GaN high electron mobility transistors on chip, which paves the way for development of nitride based superconducting device circuits.

Resume : Owing to wide band gap, GaN electronics could be operated at higher temperature than Si based counterparts. Compared to planar AlGaN/GaN heterostructure field-effect transistors (FETs), vertical FETs based on c-axis GaN NWs have advantages in logic applications. First, wrap-around-gate structure can be formed on NWs to improve gate control. Second, enhancement mode (E-mode) operation is easy to be realized on nonpolar NW sidewalls. Third, a precise doping profile can be defined by epitaxial growth vertically, while it is not easy in lateral dimensions. Finally, bottom-up grown stacked NWs can be defect free. In GaN digital IC, direct-coupled FET logic (DCFL) employing both E-mode and depletion mode (D-mode) GaN FETs offers the simplest configurations. Here, a GaN E-mode single-NW vertical FET was fabricated. The GaN NW was top-down etched with a diameter of ~420 nm, and an Al2O3 dielectric was conformably deposited by atomic layer deposition. From DC characteristics, this single-NW FET shows a threshold voltage (Vth) of >3 V and a current on/off ratio of 10^6. However, a large subthreshold swing and severe memory effects are found, which are mainly due to the interface trap and oxide charging. Moreover, GaN NW array-based D-mode vertical FETs were also made. The Vth is from -12 to -8 V due to high Si doping. Based on the results from E/D-mode GaN NW FETs, a design of vertical DCFL is proposed and we suggest GaN NW technology as a candidate for high temperature digital IC.

Resume : I will review the latest developments in the non-destructive optical characterization of III-N electronic devices. This will include GaN-on-diamond devices which are presently be developed for ultra-high power microwave electronic device applications.

Resume : ABSTRACT Due to the extremely high electric field values, GaN HEMT for switching applications are prone to physical degradation mechanisms which depend on the device design and processing [1], i.e. on the gate structure, the design of field-plates, the dielectrics and epitaxial material quality, the presence of surface and interface states. Most common physical failure mechanisms include: (i) time dependent dielectric breakdown (TDDB), occurring within gate and insulation dielectrics, in the substrate and in the semiconductor layers which form the gate stack; (ii) hot electron effects, occurring either in “hard switching” conditions [2] or during constant drain-source current stress [3]; (iii) positive (PBTI) or negative (NBTI) temperature bias instabilities of the device threshold voltage [4]-[8]. This mechanisms will be reviewed, showing how on-wafer reliability analysis can provide useful information for process and device design improvement. [1] M. Meneghini, G. Meneghesso, E. Zanoni (eds.), “Power GaN devices, materials, applications and reliability”, Springer 2017. [2] S. R. Bahl et al., IEEE IRPS, p.4A-3-1, 2016. [3] M. Ruzzarin et al., IEEE El. Dev. Lett., vol. 37 (11) p. 1415, 2016. [4] G. Meneghesso et al., Microelectronics Reliability Vol. 58, p. 151 , 2016. [5] M. Meneghini et al., IEEE El. Dev. Lett., Vol. 37 (4), p. 474, 2016. [6] I. Rossetto et al., “Performance-limiting traps in GaN-based HEMTs: from native defects to common impurities”, Chapter 9 in [1], p. 197. [7] D. Bisi et al., , “Reliability in III-N devices”, in W. Bi, H-C. Kuo, P.-C- Ku and B. Shen, “Handbook of GaN Semiconductor Materials and Devices”, CRC Taylor and Francis, 2017. [8] M. Meneghini et al., “Trapping and degradation mechanisms in GaN-based HEMTs”, in F. Medjdoub, “Gallium Nitride (GaN): Physics, Devices, and Technology” CRC Taylor and Francis, 2015.

Resume : Current-collapse is a serious problem for all GaN power transistors, especially since it can vary dramatically between apparently identical epitaxial layer designs. We discuss non-obvious features of the epitaxy that affect the current-collapse, leading to a straightforward requirement that all GaN HEMTs must meet for its suppression. Current-collapse is caused by negative charge stored in the buffer. We prove that negative charge can only be stored under static drain biased conditions if the resistivity in the layer above the charge is higher than below the charge. It follows from this very general result that negative charge storage, and hence current-collapse, can be fully suppressed by ensuring that the resistivity increases from top to bottom in the epitaxial stack. We demonstrate the effect of this simple design principle by simulating carbon doped GaN power transistors, where the resistivity of the undoped GaN channel layer is varied to be higher and lower than the carbon doped GaN buffer layer. Current-collapse is shown to change, as expected, between strong current-collapse and almost complete suppression. In the real transistor, the suppression could arise by reducing the low field resistivity of parasitic vertical leakage paths in the GaN channel layer. Such leakage paths are known to be present in devices that demonstrate low current-collapse.

Resume : Owing to its enhancement-mode operation, easy-to-obtain recess controllability and VTH uniformity, high VTH thermal stability, and especially, large gate-voltage operation range, the GaN MIS-FET with fully recessed gate structure is especially attractive for high-frequency power switching applications. Suitable gate dielectric is essential to achieve these advantages together with high reliability and stability. Recently, LPCVD-SiNx deposited at high temperature (e.g. T = 780 oC), was successfully integrated with fully recessed-gate structure to achieve high-performance E-mode MIS-FETs by employing a surface protection technique [1] during the high-temperature process. To overcome degradation (i.e. decomposition) of the etched-GaN surface in the high-T LPCVD process, a 2-nm PECVD-SiNx interfacial protection layer prepared at 300 oC is deposited on GaN prior to deposition of LPCVD-SiNx. The E-mode MIS-FET with the interfacial layer delivers large positive VTH of 2.4 V, small hysteresis and low on-resistance. Promising VTH stability of the MIS-FET has been reported [1]. In this work, we systematically investigated the bias temperature instability (BTI) of VTH in the E-mode LPCVD-SiNx MIS-FET based on combined BTI tests and drain current 1/f noise analysis. The BTI stress was carried out at several temperatures on devices with LGD = LGS = 2 μm for 104 s. VGS was set at 10 V in PBTI test and -30 V in NBTI test. The MIS-FETs deliver highly stable VTH with both small PBTI (ΔVTH = 0.2 V @ 25 oC, 0.9 V @ 150 oC) and NBTI (ΔVTH = 0.1 V @ 25 oC, 0.7 V @ 150 oC), indicating greatly improved VTH stability compared with that reported in the SiO2/GaN and Al2O3/GaN MOS-FETs. More specifically, ΔVTH follows a power law of stress time and can be fully recovered after UV illumination. The drain current 1/f noise density of the MIS-FET after recovery was not increased compared with the fresh device, indicating no additional trap states being generated at the gate dielectric/GaN interface during the long-time stress. Thus, the VTH shift observed during the BTI stress is most likely originated from the electron trapping/de-trapping process of the pre-existing traps in the gate dielectric. [1] M. Hua, et al., IEDM 2016.

Resume : Hot electron transistors (HET) are promising devices that may enable high-frequency operation that currently CMOS cannot provide. In an HET, carrier transport is due to injection of hot electrons from an emitter to a collector, which is modulated by a base electrode. Therefore, ultra-thin base electrodes are needed to facilitate ultra-short transit time. In this regard, monolayer graphene is considered the best candidate for the base layer in HETs. The existing graphene-base HETs with SiO2/Si as emitter stack suffer from low current gain and output current density. In this work, we systematically study the effect of tunnel barrier width on the on-current and turn on voltage of the base-emitter diode. The I-V characteristics show that the turn-on voltage decreases with barrier thickness. The C-V measurement shows a clear transition from depletion to accumulation for a typical GaN-based capacitor. The valleys at the accumulation region correspond to the graphene quantum capacitance, which is in series with the barrier capacitance. The presence of this feature indicates strong Fermi-level modulation in graphene near its Dirac point. The transport study of the HET shows record high output current density (>50 A/cm2), current gain (>3) and injection efficiency of 75% among the graphene-base HETs. These results indicate that performance parameters can be further improved by engineering the band offset of the graphene/collector stack and improved interface between graphene and GaN

Resume : GaN-based high-electron-mobility transistor (HEMT) with a p-GaN gate has emerged as a promising candidate for high performance enhancement-mode (e-mode) power switching devices because of its excellent figure-of-merits and robust normally-off operation. In principle, the conduction band of the AlGaN/GaN channel right below the p-GaN gate is lifted up through a P-N junction, resulting in a normally-off operation with a positive threshold voltage. While for the access region, selective removal of the overgrown p-GaN by a uniform etching is required to recover the 2-dimensional electron gas (2DEG) for a low conduction resistance. Challenge arises from the fact that either over-etching or under-etching of the p-GaN grown on the AlGaN/GaN for the non-gate region will deteriorate the 2DEG performance, as well as its uniformity, and often induce severe current collapse due to the surface damage. In this work, e-HEMTs with a p-GaN gate were successfully grown on Si(111) substrates and fabricated using a chemistry-ease Cl2/N2/O2-based inductively coupled plasmas (ICP) etching technique. This critical etching technique is featured with an etching self-termination at the AlGaN barrier surface, which enables a broad process window with a large tolerance of etching time. And the etching induced surface damage can be partially repaired by a post-annealing treatment followed by dielectric passivation, resulting in a mitigated current collapse. The as-prepared device exhibits a drain saturation current of 355 mA/mm with a threshold voltage of 1.0 V, a static on-resistance RON of 10 ?·mm, and an ON/OFF ration of 10^7. Furthermore, a high uniformity in static RON, ON/OFF ratio, and threshold voltage has been achieved across the wafer. Therefore, the as-developed technique may pave the way towards a manufacturable process for e-HEMTs with a p-GaN gate. Acknowledgements: This work was financially supported by the National Key R&D Program of China (Grant No. 2016YFB0400104), the National Natural Science Foundation of China (Grant Nos. 61534007, 61404156, 61522407, and 61604168), the Key Frontier Scientific Research Program of the Chinese Academy of Sciences (Grant No. QYZDB-SSW-JSC014), the Natural Science Foundation of Jiangsu Province (Grant No. BK20160401), and the China Postdoctoral Science Foundation (Grant No. 2016M591944). This work was also supported by the open fund of the State Key Laboratory of Luminescence and Applications (Grant No. SKLA-2016-01), the open fund of the State Key Laboratory on Integrated Optoelectronics (Grant No. IOSKL2016KF04, and IOSKL2016KF07), and the seed fund from SINANO, CAS (Grant No. Y5AAQ51001).

Resume : Using current transient spectroscopy, we show for the first time, that the conduction pathways to native deep traps in AlGaN/GaN HEMTs can be altered by 14 MeV neutron irradiation of fluence 2E13 neutrons/cm2 and above, with potential implications for device reliability and performance in radiation environments. Performance following 14 MeV neutron irradiation is critical for nuclear fusion applications, for example ITER, and is a useful indicator for nuclear fission and aerospace environment hardness. We measured on-state drain current transients in neutron irradiated HEMTs immediately following off-state electrical stress, and analysed these to gain insight into the traps in the devices, via de-trapping spectra. Off-state stress was found to trap charge in the AlGaN barrier, device surface, and buffer. Detrapping spectra are altered by the neutron irradiation: they show detrapping from deep levels following a given off-state duration, which prior to irradiation would require a longer duration of off-state bias to manifest. This suggests that neutron irradiation alters the conduction pathways by which they charge, to increase the rate of conduction to them during the off-state. This could be due to the introduction of shallow traps which facilitate trap assisted tunnelling. Comparison of 0.25 and 0.5 micrometer gate length devices illustrates how the impact of the neutron induced changes depends on the electric field magnitude. © British Crown Owned Copyright 2017/AWE

Resume : GaN based high electron mobility transistors (HEMTs) are being investigated for various applications. MOS-HEMTs have also attracted a lot of interest because of various advantages and particularly for switching applications. We have demonstrated that pre-deposition and thermal oxidation of Ti and Al can provide significant RF performance improvement. While TiO2 shows reduced interfacial characteristics in comparison to that of Al2O3. TiO2 HEMTS show much lower leakage without sacrificing RF characteristics. The observed experimental characteristics is explained from negative band offset with respect to AlGaN barrier and higher dielectric constant. The Negative shift on the threshold voltage is also found to be minimal due to higher gate coupling. We have performed systematic study on TiO2 and Al2O3 thermal oxide Schottky diodes and HEMTs. The devices are characterized for both DC and RF electrical measurements along with physical characterizations using XRD, XPS, EDX, and TEM. The superiority of performance for thermal oxide HEMTs is established which is further corroborated by simulations. The improved characteristics are attributed to the interfacial property determined through conductance spectroscopy.

Resume : GaN devices, used in recent technologies, have to handle power levels higher than 10kW. In order to satisfy this request, a novel vertical Fin FET (VFET) structure on bulk GaN substrate has been developed. In the VFET the current flows vertically through sub-micrometer multiple channels in parallel and the MOS gate stacks are placed on the sidewalls. This work investigates the trapping processes induced by positive gate stress (up to VGS = 6 V) on the dynamic performance and on the stability of VFET devices. The characterization was performed by using double pulse measurements of the drain current characteristics and constant voltage stress tests in order to identify the effects and the physical origin of carrier trapping. The effect of different temperatures on VTH and RON was investigated and 2D simulations were carried out to support the hypothesis on degradation. Two trapping processes were identified, depending on the stress voltage: when subjected to moderate gate stress (VGS < 3 V), the devices show a negative threshold voltage shift (NBTI), which is ascribed to the de-trapping of electrons from the gate insulator. The high stress bias (VGS ? 5 V) induces a strong positive shift in threshold voltage ascribed to the injection of electrons from the accumulation region towards the gate insulator. Temperature-dependent measurements support the hypothesis that only PBTI is due to a thermally activated mechanism.

Resume : There has been a growing interest in both silicon carbide (SiC) and gallium nitride (AlxGa1-xN) as next-generation power conversion devices because of their superior material properties such as larger band gap, higher saturation velocity and higher breakdown voltage than silicon (Si). We are attempting to develop a new type of vertical MOSFET with SiC/AlxGa1-xN heterojunction as a next-generation power conversion device. One of the prerequisites for the realization of the vertical MOSFET is that the conduction-band offset (CBO) of SiC/AlxGa1-xN interface is small enough to eliminate the interface scattering when electrons go across the interface. Therefore, we calculated the CBO of SiC/AlxGa1-xN interface by the first-principles calculation code based on the density-functional theory, and we clarified the condition that the CBO became zero. We made 4H-SiC/AlxGa1-xN 2x2 interfaces mimicked by the superlattice models. However, the models have saw-toothed electric fields perpendicular to the interfaces owing to the superlattice structure. We found that the unfavorable fields were removed by taking into account the electron-counting model of covalent bond and then the CBO were evaluated successfully. In addition, we calculated the CBO of SiC/AlxGa1-xN with AlN/GaN short period superlattice structures proposed by Suda group. As a result, we observed that the offset value decreases with increase in Al content and the Al content where the CBO becomes zero is about 75%. Therefore, 4H-SiC/Al0.75Ga0.25N interface is one of the most promising candidates for the vertical MOSFET in future power conversion devices.

Resume : The SiNx layers on the (0001)AlN surface were in situ grown by ammonia MBE. The SiNx formation processes on the surfaces of AlN/GaN structures were investigated by RHEED and XPS methods. For the initial N-rich AlN surface the pinning of Fermi level by nitrogen induced donor-like states at 1 eV above the valence band maximum of AlN (VBM) was observed. The deposition of single SiNx monolayer onto AlN surface results in appearance of a (sqrt3 x sqrt3)-R30° surface reconstruction. Corresponding XPS data demonstrate that the VBM is shifted to 2.1 eV below the Fermi energy. Further deposition of silicon nitride leads to amorphous silicon nitride phase formation, meanwhile the VBM gradually downs to about 3.1 eV below the Fermi energy. Note, that the N/Si ratio founded by XPS is about 1.28 for the formed SiNx layer, instead of 1.33 known for the Si3N4. The observed behavior of VBM energy position during the SiNx deposition was explained by formation of donor-like K-centers related to silicon dangling bonds of Si-rich SiNx layer. 2DEG gas was found in these SiNx/AlN/GaN heterostructures with electron mobility of 1200 cm2/Vs and concentration of 1.5E13 cm-2. Current collapse effect was not detected in the enhanced-mode transistor fabricated on the base of SiNx/AlN/GaN heterostructure.

Resume : Owing to its high breakdown voltage of 3 MV/cm and wide band gap of 3.4 eV, GaN offers many advantages over Si for power electronics and can lead to higher efficiency and substantial size reduction of electronic devices. A novel vertical field-effect transistor (FET) technology based on 3D GaN nanostructures combines the superior properties of GaN nanostructures with the vertical device architecture required for high-power operation. Our first devices using top-down-etched GaN nanowire arrays have shown enhancement-mode operation (normally off) with already impressive device performance such as on/off current ratio of 10^8, subthreshold slope of 68 mV/dec, drain current of 314 mA/mm and transconductance of 125 mS/mm. Here, an improved design is presented. By replacing nanowire structures with fin arrays, the 3D vertical FET devices can obtain higher mechanical stability, better reproducibility and less edge effects. High-aspect-ratio fins with almost defect-free sidewalls have been grown using metalorganic vapour phase epitaxy (MOVPE) on prepatterned GaN on sapphire templates. The growth of vertically stacked pn-junctions required for higher breakdown voltages is currently being investigated. Moreover, to have a direct quality comparison, a hybrid etching technique is employed combining inductively coupled plasma reactive ion etching (ICP RIE) and wet chemical etching to realize similar structures of 3D top-down vertical fin arrays from planar GaN substrates.

Resume : We have investigated the temperature and frequency dependent capacitance-voltage (C-V) characteristics of AlGaN/GaN HEMTs grown on 6-inch silicon with a carbon-doped buffer. On increasing the temperature, a broadening of capacitance dispersion with respect to frequency was observed in the depletion region. Though there was a significant positive shift in the threshold voltage (Vth) with increasing T in C-V characteristics, the same was not observed in the DC IDS-VGS characteristics. This could be attributed to the negligible temperature dependence of the steady-state 2DEG concentration. In the depletion region, the G/W vs frequency plot has two peaks, each corresponding to a pair of interface trap density (Dit) and trap time constant (Tit). One pair of Dit and Tit values ranges from 1-5x10^12/eVcm2 and 1.1-13 µs while the other pair exhibits Dit-Tit in the range of ~0.07-4X10^12/eVcm2 and ~0.1µs at 25°C respectively. In the accumulation region, the Ni/AlGaN interface was probed and the Dit and Tit were estimated to be 0.52-21x10^13/eVcm2 and 0.06-0.9 μs respectively at 75°C. The hole emission mechanism that was invoked to explain the Vth shift in the C-V characteristics will be presented along with the pulsed I-V and breakdown dependence on temperature. The work is funded by the Ministry of Electronics and IT under its National Mission on Power Electronics Technology program and by an EPSRC Programme Grant for Silicon Compatible GaN Power Electronics.

Resume : We report on the study of Al2O3/InAlN/GaN HEMT interface grown on 200 mm diameter Si using capacitance dispersion technique. The as-grown 2DEG density (~ 2x10^13cm-2) of devices was found to be depleted partially after gate deposition, forming gas anneal and electrical stress. The growth interruption for InAlN low temperature growth is likely to give rise to high trap density at the InAlN/GaN interface which when activated, can lead to partial depletion of 2DEG as evident from 1D-Schrodinger-Poisson simulation supported by experimental data. Traps at Al2O3/InAlN and InAlN/GaN interface were probed in accumulation and depletion region respectively and corresponding trap density (Dit) and trap time constant (Tit) were estimated using conductance method. Traps at Al2O3/InAlN and InAlN/GaN interface were found to be in the range of 0.4-7x10^13 eV-1cm-2. While trap time constant for Al2O3/InAlN interface was around 2.2 μs, almost constant time constant at the dielectric-InAlN interface confirms the robust dielectric-semiconductor interface. The work is funded by Ministry of Electronics and IT (MeitY) under its National Mission on Power Electronics Technology (NAMPET) program.

Resume : III-Nitride based High Electron Mobility Transistors (HEMTs) are among the devices with best potential for high power and high frequency device applications. The material has received lots of attention due to its appropriate properties for high power and frequency applications. The surface states under the gate and access region play a vital role in the device performance and reliability. Enormous amount of research is carried out to study and decrease the surface/interface states. However, achieving the surface and interface, without any trap states in AlGaN/GaN are still a challenge. Schottky gate contact is a very important building block of the transistor. Post gate annealing of AlGaN/GaN HEMTs in N2 ambient at relatively low temperature (~400-450oC) improves the reverse leakage current and reverse breakdown voltage of the Schottky contact due to the reduction in shallow trap states (Wu Lu et.al.). Here, we have used N2 plasma treatment prior and post to the Schottky gate metallization to further enhance the effect of N2 annealing. Schottky diodes and HEMTs devices are fabricated on AlGaN/GaN hetero-structures having 2-DEG density and electron mobility of 7x1012 cm-2 and 1629 cm2V-1s-1 respectively. Sub-threshold leakage current and gate leakage current are suppressed by around two orders of magnitude for the N2 plasma processed devices. The gate reverse breakdown voltage (with gate current set to 0.2 µA/mm) was observed to be more than -100V (out of measurement scope) as compared to -4V for the device without N2 plasma treatment. Knee voltage for the gate Schottky junction is shown a shift of around 1V toward the positive direction. These improvement provides scope for wider voltage range of operation for these devices without breaking down. Pulsed-IV with pulse-width varying from 150 ns to 1ms measurement shows least current dispersion with respect to DC-IV for the N2 plasma based devices. This indicates the reduction of traps due to N2 plasma treatment which are more effective in passivation of the surface states.

Resume : High vertical leakage current and low vertical breakdown voltage are predominant concerns for AlGaN/GaN HEMTs on Si. Although several literatures have studied the vertical leakage/breakdown mechanisms, all the results concentrate on the vertical transport behaviors under pure vertical bias condition only. In fact, during power operation, devices are inevitable to undergo a semi-on condition characterized by both high lateral and vertical voltage. During the condition with high lateral electric field, 2DEG electrons are accelerated as hot electrons which may assist vertical leakage/breakdown. Thus, there is a strong motivation to investigate the physical mechanisms behind. We present a hot electron assisted vertical leakage/breakdown mechanism in AlGaN/GaN heterostructures on Si substrates by a combination of applying vertical and lateral bias conditions. Beyond a critical bias point, the vertical leakage current under the combined bias condition is larger than that under a pure vertical bias condition which results in a lower breakdown voltage. The critical bias has a positive temperature dependence. A model is proposed that highly energetic hot electrons can release trapped electrons from defects and even ionize them. The model is proved by investigating the detrapping and ionization mechanisms by changing hot electron energy. The trap state responsible for the trapping/detrapping phenomenon is found with an activation energy of ~ 0.38 eV.

Resume : Vertical Schottky diodes formed on GaN free-standing substrates have been intensively studied for high-power applications. Controlling low-carrier-concentration in a thick drift-layer is a key issue in this structure. In this study, we characterize the effect of the surface morphology on the n-GaN drift-layer by using scanning internal photoemission microscopy (SIPM). We grew 11-micron-thick n-GaN (Si: 1E16 cm-3) layers on free-standing GaN substrates by MOCVD, and formed Au/Ni Schottky contacts (200 microns in dia.). When a monochromatic light with a photon energy exceling Schottky barrier height is incident on a metal/semiconductor interface, electrons in the metal can surmount the barrier generating a photocurrent based on the internal photoemission effect. In the SIPM measurements, one focuses and scans the beam over the interface to obtain 2-dimensional imaging of the photocurrent. We conducted SIPM measurements for the Ni dots formed on the wavy n-GaN surface with red, and green lasers. The photocurrent maps clearly showed the same pattern as the surface morphology. Since a large yellow-luminescence signal in PL was detected where the photocurrent was small, this pattern indicates the variation of the carrier compensation by incorporated C atoms during the growth, which has a correlation with an off angle of the GaN substrate. We demonstrated that SIPM is a powerful tool to nondestructively visualized inhomogeneity of the carrier compensation over the contacts.

Resume : GaN is a promising semiconductor to replace silicon for power applications due to its wide bandgap, large critical electric field, high electron mobility and saturation velocity. Vertical GaN devices fabricated on freestanding GaN with a reasonably low threading dislocation densities (10^4–10^6 cm^-2) were recently reported with an excellent voltage and on-resistance tradeoff. However, high quality bulk GaN substrates are expensive, and GaN heteroepitaxy on foreign substrates results in material with high dislocation densities, hindering the development of vertical GaN power devices. In this work, we describe fabrication procedure and characterisation of Schottky diodes with an active region in the formed using dense 2D uniform array of GaN nanocolumns (NC). The NC architecture was first explored using finite element analysis from first principle calculations and theoretically achieves blocking voltages upwards of 1200 V with a very low specific on-resistance. This can be achieved due to dislocation-free NCs and dielectric reduced surface field in NCs surrounded (in-filled) with a dielectric. Preliminary experimental results on such Schottky diodes then showed that the first not yet optimised devices exhibit a distinct rectifying characteristics with breakdown voltage around 100 V and no signs of current collapse. Although more work is needed to further explore the nano-GaN concept, these results indicate that superior tradeoff between the breakdown voltage and specific on-resistance can be achieved, all on a vertical architecture. The proposed NC approach has a potential to deliver low cost reliable GaN power devices, circumventing the limitations of today’s lateral geometry devices.

Resume : Charge trapping in the buffer leads to a significant current collapse in AlGaN/GaN power HEMTs. Thus, it is necessary to understand the charge storage and current transport in various layers of the buffer to predict the long-term stability of such devices. Dynamic RON and ramped substrate bias measurements are used to demonstrate size and geometry dependent dispersion in different wafers. This is shown to be the result of a lateral transport mechanism in the semi-insulating carbon-doped GaN buffer. We propose a model explaining that the vertical field results in the formation of a 2D hole gas (2DHG) layer at the heterojunction between the bottom of the GaN:C layer and the AlGaN strain relief layers, with hole flow extending outside the isolated device area. The spread of this 2DHG outside the active area of the device affects the results of substrate ramp measurements producing major differences between single and multi-finger devices. In dynamic RON recovery measurements, single-finger devices show large device-to-device variation, with multi-finger devices showing a small variation with the transient comprising the superposition of the recovery transient of multiple small single-finger devices. This variation is due to a combination of widely spaced (100?m separation) preferential leakage paths through the structure and lateral transport from those paths to trapping sites.

Resume : The development of GaN-based technology has progressed rapidly over the last decade with a remarkable increase in device performances. While these results are promising, several problems such as poor yield, devices premature fail, and reliability issues still hinder large scale commercialization and full adoption of GaN-based technology. In this works, we reports on the reliability study of gate recessed Normally-On and Normally-Off AlGaN/GaN MOS-HEMTs. In order to obtain the e-mode behavior, the AlGaN barrier, under the gate electrode, was thinned down using digital etching process. Using this soft gate recess approach, the threshold voltage (Vth), defined at Ids=1µA/mm, was accurately modulated from -2V to +1.1V without inducing significant damages on AlGaN surface. This was confirmed using AFM analyses and corroborated with devices electrical characteristics (low hysteresis, high Ion/Ioff ratio, low Ron, etc.). To evaluate the reliability of the fabricated transistors, extended stress measurements were performed under thermal and electrical stress. Devices performances are systematically monitored and the evolution of the main parameters (Vth, Ron, Vknee, Ids-max and Ileak) are discussed. The characteristics of TDDB (time-dependent dielectric breakdown) and SILC (stress-induced leakage current) for the SiO2 gate dielectric layer are studied. The degradation mechanism, during the stress cycles, will be presented and correlated with reported defects generation mechanisms.

Resume : Wide bandgap AlGaN/GaN HEMTs are emerging as excellent candidates for high-power and high-frequency applications, featuring high saturation current, and high breakdown voltage. An AlGaN/GaN HEMT based on an ultra-thin AlGaN barrier layer with high aluminum content is used in this work. This heterostructure is capped with an in-situ SiN layer which is needed to reduce the sheet resistance. However, this SiN layer should be selectively removed under the gate electrode to modulate the threshold voltage. In this study, we report a new approach to selectively remove the SiN layer without using fluorine-based plasma. Indeed, the SiN cap layer cannot be commonly removed using a wet etching. So, fluorine plasma is used to remove it before depositing the gate electrode. This process creates surface damage affecting the device performances (Vth shift, hysteresis, current collapse, gate and drain lag). We develop a new process avoiding any exposition of the AlGaN layer to fluorine plasma. This consists on a local modification of the SiN layer using a soft hydrogen based plasma followed by a wet chemical etching of the modified SiN. FTIR measurements show that H-plasma induces the formation of N-H and Si-H bonds in the SiN, making its etching rate faster by a wet chemical treatment. The detailed modification/etching mechanism will be discussed further and a comparison between the fabricated HEMTs devices, using the new H-based approach and the common F- based plasma, will be presented.

Resume : Gallium nitride (GaN) is a promising semiconductor for high power device applications. To realize high breakdown voltage in power devices, the impurity concentration of the drift layer should be low. Additionally, m-plane GaN is expected to improve mobility in case of fabrication of vertical devices. Compared with c-plane GaN, however, large amount of impurities are incorporated in non-polar m-plane GaN. Metalorganic vapor phase epitaxial growth of GaN on m-plane GaN substrate with 0.2° toward the [0001] off-cut angle was performed at atmospheric pressure with a V/III ratio of 1000 and substrate temperature of 1100°C. We achieved a drastic reduction of impurities by using a quartz-free reactor. For example, oxygen, carbon, and silicon concentrations were reduced from O: 2e17, C: 2e17, and Si: 5e15 /cm^3 to O: 2e16, C: 1e16, and Si: 4e15 /cm^3, respectively. Subsequently, we found a reduction in oxygen concentration from 2e16 /cm^3 for the 2um-thick sample to 7e15 /cm^3 for the 15um-thick sample. As a result, we achieved a high breakdown voltage of over 1.6 kV in Schottky barrier diodes. The detailed characteristics of the Schottky barrier diodes in m-plane will be discussed. Acknowledgement: This work was partly supported by the “Super Cluster Program” of the Japan Science and Technology Agency.

Resume : High quality metal-oxide-semiconductor (MOS) gate stacks with stable threshold voltage are required for future GaN-based power transistors. Here, we report a route to the realisation of GaN MOS-capacitors (MOSCAPs) which avoids air exposure of the GaN surface by utilising in-situ deposition of SiNx as the final part of substrate growth, and clustered plasma etch and atomic layer deposition (ALD) tools. The optimised process developed in this work enabled a ~4x reduction in flatband voltage hysteresis, indicative of a significantly improved GaN-dielectric interface. The Metal Organic Chemical Vapour Deposition grown wafer of this study included a 600 nm 1x1017 cm-3 n-doped GaN layer which was capped with 5 nm SiNx. The samples were etched using reactive ion etching (RIE) in a SF6 plasma (50 W, 50mT, 45 s) in the etch chamber of the cluster tool to remove the SiNx before transfer under vacuum to the ALD chamber where, following N2 plasma treatment (5 mins 150 W), 20 nm of Al2O3 was deposited using a 2000C thermal TMA/H2O process. Au-based metal contacts were deposited ex-situ before the MOSCAPs were evaluated by room temperature 1 MHz capacitance-voltage measurement. This comprised a voltage sweep from -5V to +5V and then back to 5V, enabling the determination of flatband voltage hysteresis of 60 mV, significantly lower than in [1] where 250 mV was reported for MOSCAPs without an in-situ SiNx capping layer. [1] S. J. Cho, et al., Microelectron. Eng.147, pp277-280 (2015)

Resume : SiON would be an alternative candidate to take good properties from both SiO2 and SiNx. In this study, we have developed a high quality SiON deposition process using a plasma enhanced chemical vapor deposition system for the gate insulator of normally-off AlGaN/GaN-on-Si recessed metal-insulator-semiconductor heterostructure field-effect transistor (MIS-HFET). SiON films were deposited at 350°C using SiH4, N2O, and NH3 mixtures as reactant gases. The optimum deposition conditions are gate flow rates of (SiH4/N2O/NH3 =50/25/25 sccm), a source RF power of 100 W, and a chamber pressure of 500 mTorr. The optimized SiON film had a breakdown field of 12 MV/cm and a dielectric constant of 5.3. The fabricated normally-off device exhibited a threshold voltage of ~2 V, an on-resistance of 7.85 m??cm2, and a breakdown voltage of 893 V. The device had excellent characteristics in both pulsed I-V and dynamic on-resistances. The dynamic on-resistance was increased by only 1.43 times at VDD = 200 V. In order to investigate the threshold voltage instability for SiON MIS gate, gate bias stress tests were carried out up to 150°C. Change in threshold voltage was ~0.5 V after 10 V gate bias stress at 150°C. Though further optimization is necessary, it is suggested that the SiON film is a great candidate for the gate insulator of AlGaN/GaN MIS-HFETs.

Resume : High electron-mobility transistors (HEMTs) based on Gallium Nitride (GaN) have demonstrated tremendous performance for RF power and power electronics. Due to the high level of power for the applications intended, self-heating prediction and management is of paramount importance for the device overall performance and reliability [1]. Diverse optical and electrical techniques are commonly used for steady-state temperature measurement. Nevertheless, few works have been done for determination of time-dependent self-heating although it concerns some major applications such as pulsed-RF operation, RF amplitude modulation and power switching. In this work, we use two experimental methods based on electrical measurement to determine a MOS-HEMT GaN transient self-heating. Both techniques uses gate resistance measurement, the first in frequency domain [2] from 1 Hz to 10 MHz and the second in time domain with a time resolution of 200 ns. Special consideration is given for the extraction procedure and instrumentation. The results are compared with finite-element simulation and a thorough analysis is conducted. Finally, a compact Cauer model developed on Keysight ADS and suitable for further design consideration is introduced. [1] J. Cho et al., ?Near-junction thermal management: Thermal conduction in gallium nitride composite substrates? Annu. Rev. Heat Transf., vol. 18, 2014. [2] A. Cutivet et al., doi: 10.1109/LED.2016.2641740

Resume : We demonstrated a 1 MHz DC-DC converter using a clamped AlGaN/GaN metal-oxide-semiconductor heterojunction field-effect transistor (MOS-HFET) in which a clamp circuit consisting of a diode and a capacitor was monolithically integrated with normally-on AlGaN/GaN MOS-HFET. The integrated clamp circuit enabled a normally-on FET with a negative threshold voltage to be operated just like a normally-off FET with a positive threshold voltage. In comparison with other conventional normally-off GaN-based FETs, a higher threshold voltage with high current density can be achieved and the threshold voltage can be controlled simply by the gate insulator thickness. A 10 nm SiO2 MOS gate resulted in a pinch-off voltage of -7 V from which the converted virtual threshold voltage was 2.3 V using a gate input signal of 10/0 V. It should also be noted that the monolithic integration of a clamp circuit into an FET minimized the parasitic inductance, which, in turn, suppressed the over-shoot effects improving the safety operation area and conversion efficiency. Detail switching characteristics of the fabricated clamped MOS-HFET will be presented along with 1 MHz power conversion characteristics of a DC-DC converter implemented with the clamped device.

Resume : An AlGaN/GaN heterostructure field-effect transistor (HFET) as the next-generation power device has lots of advantages such as high efficiency, high frequency, and high power [1]. These advantages are enabled by the high electron mobility and density of the 2DEG layer formed naturally at the interface between AlGaN and GaN. It is known that the surface of AlGaN is sensitive to atmosphere, so easily aggravates the electron density in 2DEG. Applying a passivation layer on top of AlGaN can mitigate this issue, so called the passivation effect, however, the underlying physics related to the passivation effect has not been fully examined yet. In this study, we present a systematic study on the effect of passivation layers on carrier transport in AlGaN/GaN HFETs by means of various passivation materials and deposition techniques. We deposited a 100 nm thick SiO2 or SiNx layer on AlGaN/GaN surface by using PECVD or rf-sputter system. For comparison purpose, a sample without any passivation layer was prepared at the same time. We found that the sheet carrier density of the samples with a passivation layer (either SiO2 or SiNx) deposited by using PECVD increased, compared to the reference sample; while the sheet carrier density of the samples with a passivation layer deposited by using a rf-sputter system decreased. Through a PL measurement and Raman analysis, we found that the carrier transport in 2DEG of an AlGaN/GaN HFET is significantly influenced not only by a passivation material itself but also by a deposition method. These findings will be useful for the further optimization of passivation layers for the various applications of AlGaN/GaN HFETs. [1] O. Ambacher, J. Smart, J. Shealy, N. Weimann, K. Chu, M. Murphy, W. Schaff, L. Eastman, R. Dimitrov, and L. Wittmer, J. Appl. Phys. 85, 3222 (1999).

Resume : GaN Schottky barrier diodes (SBDs) have shown great potential for high temperature, high power and high frequency applications . This paper presents the design, fabrication and measurement of the GaN planar SBD using the air-birdge Technology and electroplating Technology to reduce the parasitic parameters. The GaN materials consists of an 1-μm n+ GaN layer (~3×1018 cm- 3) and a 200-nm n- GaN layer (~1×1017 cm- 3). An ohmic contact resistance of 0.15 Ω·mm is obtained with a Ti/Al/Ni/Au(20nm/130nm/50nm/150nm) metal stack which is about 40% lower than that of a Ti/Al/Ti/Au(20nm/60nm/50nm/70nm) metal stack. Also, compared to diluted BOE solution, the better ohmic contact can be arrived by employing HCl+HF solution, for the n+ GaN surfaces chemical treatment. GaN-based SBD devices with various anode diameters(3-7μm) are fabricated on the same conditions. The fabricated GaN SBD diodes were characterized by I-V and C-V measurements at DC. The zero bias junction capacitance and the series resistance are calculated for different anode diameter. We find the extracted ideality factors and schottky barrier heights for those SBD devices showed dependence on the anode area. The extracted ideality factors for the SBDs with various anode diameters(3, 5, 7μm) are around 2.46, 1.89 and 1.37, respectively. On-wafer small-signal S-parameter measurements are also performed up to 50 GHz. A cut-off frequency (fc) of 627 GHz is achieved for GaN planar SBD with 7 μm anode diameter.

Resume : GaN-based high-frequency devices and power switching devices have attracted much attention. To improve their device performance, understanding and reduction of not only electron traps but also hole traps are essential. There are some reports on hole traps by using optical excitation (ODLTS), which mainly focused on a thermal emission process. In this study, we investigated hole traps in n-type GaN by ODLTS focusing on the optical excitation process. Dependences of ODLTS signal on wavelength of excitation light, irradiated photon flux, bias voltage, temperature and size of electrodes were investigated. The samples used were MOVPE-grown n-type GaN homoepitaxial layers with Ni Schottky contacts. First, isothermal ODLTS was performed using sub-bandgap light (365-450 nm). For all wavelengths, hole traps (H1, Ev+0.85 eV) were detected. Next, we investigated the time constant of optical excitation (electrons at the H1 level to the conduction band, resulting in holes occupation at the H1 level) under various excitation photon flux of 405 nm at 300 K. Inverse of the time constant was proportional to the excitation photon flux, indicating that the optical excitation of electrons is dominant. On the other hand, at 360 K, the proportional relationship was not observed. It is partly explained by an increase in a thermal emission rate of holes from the H1 level to the valence band during the optical excitation period. We will discuss rate equation analyses to explain our observation.

Resume : GaN has attracted much attention for their potential applications in power electronic devices, benefitting from its superior properties, such as wide band gap, high electron mobility, large breakdown field and high thermal conductivity. A vertical structure is believed to be more suitable for high-power applications than lateral devices since high current and voltage can be achieved simultaneously with reduced on-resistance and less effect from surface/interface states. Moreover, the fast development of free-standing GaN substrates with low threading dislocations (TDs) density (on the order of 106 cm-2 or less) in recent years opens up an opportunity for the GaN vertical-type power conversion applications. Compared to PN junction diodes, the Schottky Barrier diodes (SBDs) are expected to achieve both low on-resistance (Ron) and turn-on voltages (Von) since they do not have minority carrier storage issue and have higher electron mobility. However, currently, there is no report on the vertical-type SBDs with both low Ron and Von. On the other hand, the breakdown voltages of the SBDs are still far from their ideal value, and its breakdown mechanism is still unclear. In this study, the vertical-type Schottky barrier diodes (SBDs) were fabricated from the metal-organic chemical vapor deposition-grown GaN epitaxial layer on free-standing GaN substrates. It was found that the quality of GaN drift layers and SBDs properties were strongly dependent on the growth rates. The mobility as high as 1370 cm2/(V·s), step-flow surface morphology, near unity ideality factor (n~1.04) and high Schottky barrier height (~0.97 eV) were achieved at a relatively lower growth rate of 2.61 μm/h. An extremely low turn-on voltage (0.73 V) together with the low on-resistance of 0.72 mΩ·cm2 was obtained. The breakdown behaviors were investigated by emission microscopy and it was found that the first breakdown happend at the anomalistic pits with mixed-type dislocations.

Resume : GaN-based Schottky Barrier Diodes (SBDs) are booming because of their great potential of high frequency and excellent power-handling capability. In this paper, AlGaN/GaN hyterojuction structure was grown on sapphire by MOCVD with 2DEG density of ~9×10^12 cm^2. Two kinds of AlGaN/GaN Lateral Schottky Barrier Diodes with the air-bridge structure have been fabricated. The difference between the two diodes is that, one is metal-AlGaN Schottky contact and the other is metal-2DEG Schottky contact with recessed structure. The influence of both Schottky contacts was investigated after DC and RF test. It is found that the ideal factor and turn-on voltage (Voltage where the current is 1uA) decrease with the recessed metal-2DEG Schottky contact from ~3.18 and ~0.95V to ~2.62 and ~0.22V, respectively. While the reversed saturation current increases from 1.2×10^-11A to 7.2×10^-8A. The current increasing rate d(lnI)/dV with recessed structure is 1.21 times that of non-recessed structure at nonlinear region. C-V curve has been measured by using spectrum analyzer. The total parasitic capacitance (Cp) of recessed structure rapidly reduces from ~188.4fF to ~14.8fF as the Voltage decreases from 0V to -1.5V; when V<-1.5V, the variation slope of Cp is gentle, and Cp decreases to ~5.17fF@-10V; when V<-10V, Cp rarely changes along with Voltage.Both SBDs reveals the same trend of C-V curve. Cp shows a rapid variation on high frequency region, which reveals a great potential of high-rank multiplier.

Resume : AlGaN/GaN high electron mobility transistors (HEMT) are key devices for the next generation of high-power, high-frequency and high-temperature electronics applications. Although significant progress has been recently achieved, both the high gate leakage current and current collapse are still some of the main issues under investigation. Insulated-gate and surface-passivation structures are inevitable to mitigate these challenges. However, Gao et al have recently proposed that the water-related redox play a significant role in the physical origin of surface trapping states both in unpassivated and passivated AlGaN/GaN HEMTs[1]. Therefore, a robust solution to avoid water adsorption and diffusion is still under research. In this work, we analyze the impact of a 2D graphene layer on top of the SiN passivation layer of AlGaN/GaN metal–insulator–semiconductor HEMTs (MISHEMTs), under harsh enviroments. Results showed that in the devices without the graphene layer, ID,max and gm,max decreases gradually as the H2O vapor exposure time increased, up to 23% and 10%, respectively. Moreover, the gate lag ratio (GLR) increased around 10% during H2O vapor exposure. In contrast, the devices with a graphene layer showed a robust behavior and not significant changes in the electrical characteristics in both DC and pulsed conditions. The origin of these behaviors has been discussed. [1] F.Gao. JAP 115, 124506 (2014). Ack: MINECO proj. GRAFAGEN (ENE2013-47904-C3) and JdC-I prog. (IJCI-2014-19473).

Resume : Over the past decades, III–nitride based high-electron-mobility transistors (HEMTs) have been demonstrated in high power and high-frequency electronic devices owing to their superior material properties, such as high electron saturation velocity, high critical breakdown voltage, and polarization induced two-dimensional electron gas (2DEG). However, AlGaN=GaN HEMTs suffer from low reliability related to buffer leakage in the GaN BL due to an unintentional n-type property caused by nitrogen vacancy (VN) and impurities. Therefore, a poor pinch-off characteristics will degrade the rf performances of the HEMTs at high frequency. To prevent buffer leakage, many groups have been studied the effective doping method. The carbon and iron were widely used for fabricating the high resistivity GaN buffer layer (BL). Generally, carbon and iron have been known for an acceptor substituting on nitrogen site (CN) and substitution into gallium (FeGa). These deep acceptors compensate with the background donor. Moreover, the deep level generated in the near midgap works electron trapping center such as C-related complexes, CGa, Fe2 , and Fe3 . Therefore reliable device performance can be obtained by these GaN BL. However, these dopants cause distortion of crystal quality because the GaN BL requires heavy doping for compensation due to the high ionization energy. As an alternative, Mg doping would be a better candidate for compensating dopant because Mg has lower ionization energy than other dopants. Therefore Mg doping can reduce the distortion of crystal quality in GaN BL. The detailed comparison of these dopants is shown in Table I and Fig. 1. However, most studies have been focused on the realization of high hole concentration, the high crystal quality, and low resistivity in the Mg doped GaN. Only a few studies have been reported on Mg doping in AlGaN/GaN HEMTs. In this paper, we report the Mg-compensation effect in GaN BLs for semi-insulating (SI) BLs in AlGaN/GaN HETMs. reference : [1] Jpn. J. Appl. Phys. 56 015502 (2017)

Resume : III-Nitride based MISHEMTs are attractive due to reduced gate leakage, particularly for fabricating enhancement mode devices. Al2O3 is a very suitable dielectric material because of its appropriate material properties such as large band gap (7-9 eV), higher dielectric constant (8.0-9.5), breakdown field (>10 MV/cm) and suitable band alignment with GaN. The quality of the oxide and oxide/III-Nitride interface is of extreme interest of research. Atomic layer deposition (ALD) are normally used to grown Al2O3 as a gate dielectric for its proven quality oxide. However, wet oxidation of AlGaN barrier layer using hydrogen peroxide (H2O2) received significant amount of attention due to its reduced process complexity and found very suitable to be used as a gate dielectric. Here, we have used post dielectric N2 plasma treatment to further improve the quality of wet grown Al2O3 oxide. Sample is dipped in to the H2O2 solution after gate lithography followed by N2 plasma treatment. Various performance parameters of the fabricated HEMTs are used to corroborate the improvement in the oxide and oxide/AlGaN interface quality. Longer gate length of 500 nm are used for better comparisons. Gate leakage current is found to be suppressed by an order of magnitude and sub-threshold leakage is observed two orders of magnitude lower for the N2 plasma processed devices. Both of these parameter are important to decide subthreshold characteristics such as subthreshold slope (SS) and ION/IOFF. SS is reduced to the half and ION/IOFF is improved by two order of magnitude compared to without N2 processed devices. They are the key parameter to assure linearity, power added efficiency, reliability and noise figure in power amplifier. Post dielectric N2 processed sample proved to have better gate control over the channel.

Resume : A series of AlGaN/GaN-based high electron mobility transistor (HEMT) heterostructures was grown on sapphire substrates by ammonia MBE using STE3N2 system (SemiTEq). Stack of buffer layers of the grown heterostructures comprised AlN, AlxGa1-xN (x~0.3 and x~0.1) layers distinguished by composition-modulated AlGaN layers, in which Al content reduced toward a top of a heterostructure gradually. Within the series, growth conditions of the buffer layers were varied. Photoluminescence and stimulated emission measurements were performed. A roughness of the heterostructure surfaces was evaluated by scattered emission intensity of excitation laser. Photoreflectance measurements were applied to determine internal electric field in GaN layer. 2DEG mobility and concentration were measured using Lehighton 1605 contactless Hall system. Correlations of photoluminescence, stimulated emission and photoreflectance properties of the HEMT heterostructures with 2DEG performances and with growth conditions of the buffer layers are discussed. Waveguide properties of the grown heterostructures were calculated using the plane wave approximation. It was shown that the fundamental mode has the maximal optical confinement factor compared to high-order modes. Based on the theoretical investigations, it's concluded that lasing performances, being very sensitive to roughness of heterointerfaces and imperfection of the GaN active layer, can be used as a criterion of the HEMT heterostructure quality.

Resume : Advanced applications of AlGaN/GaN high-electron-mobility transistors (HEMTs) are driving a need for an insulated gate technology. We present here basic and early applied studies of zirconium oxide (ZrO2) as a high-k gate dielectric for reduced gate leakage and application in a fully-recessed barrier structure for enhancement-mode operation. We report on GaN surface preparations for dielectric deposition, surface/interface characterization and device operation wherein a world record threshold voltage of +3.99V is achieved. We’ve shown that GaN surfaces treated with a piranha etch followed by thermal oxidation give the best performing interfaces with atomic layer deposited (ALD) high-k dielectrics [1]. This same preparation is applied to ALD ZrO2 dielectrics deposited using different metal precursors [zirconium (IV) tert-butoxide (ZTB) and tetrakis(dimethylamido)zirconium(IV) (TDMAZ)] and water. ZrO2 films grown with ZTB were slightly oxygen rich while films grown with TDMAZ were stoichiometric. ZTB films on optimally prepared surfaces shown the best performance in terms of smoothness, low leakage in forward and reverse bias (< 10-5 A cm-2) and low hysteresis. Compared to previous studies with ALD deposited Al2O3 and HfO2, ZrO2 films show considerably higher trapped charge densities. The nature of this charge is unknown at this time but believed to be due to excess oxygen in ZTB deposited films. [1] C.R. English, et al., J. Vac. Sci. & Technol. B 32,03D106 (1-17) (2014).

Resume : Current spreading in LEDs can be improved by using transparent conducting oxides (TCOs) as contact layers. However, the work function of many TCOs make them unsuitable for this purpose in GaN-based LEDs. This paper reports a study of the effect of a thin metal interlayer between ZnO:Al (AZO) layers deposited on the p-type GaN layer of green InGaN/GaN LEDs using local current-voltage (I-V), electroluminescence (EL) and electron beam induced current (EBIC) methods. The thin metal interlayer inserted between AZO and p-GaN layer is shown to suppress the contact resistance while maintaining good transparency. Current-/conductivity-voltage characteristics showed the LEDs had sufficiently low turn-on voltage for good functionality. Static EBIC maps acquired at beam energy of 15-20 keV showed near constant signal across the AZO contacts. However, image post-processing of the EBIC maps revealed inhomogeneity in the signal intensity across the LED which correlated with variations in emission intensity observed in micron-scale EL maps. Comparison of EL maps taken at low current with EBIC maps acquired in pulse mode revealed that the intensity variation was caused mostly by spatial fluctuations in the IQE of the MQW and not variations in the contact resistance or p-type doping density in the GaN. This result revealed the combination of AZO with a thin metal interlayer to be a promising indium-free transparent contact technology. This research has received funding from the European Union?s Horizon 2020 research and innovation programme under grant agreement No 641864 (INREP).

Resume : Recently, graphene (Gr) integration with Nitride semiconductors (III-N) has been considered to implement novel device concepts for ultra-high frequency applications. As an example, Gr/AlGaN/GaN heterostructures can represent the key building block for a Gr-Base Hot Electron Transistor (GBHET), a vertical device where Gr plays the role of the ultrathin base and the AlGaN/GaN 2DEG of the emitter [1]. Here, we explored two approaches to fabricate Gr/III-N heterostructures: (i) the transfer of Gr grown by CVD on catalytic metals (Cu) [1]; (ii) the direct CVD growth of Gr on AlN and AlGaN/GaN templates on different substrates (Si, SiC, sapphire), as well as on bulk AlN [2]. Several characterization techniques were used to investigate the heterostructures: structural analyses (XRD and atomic resolution STEM/EELS), XPS and LEED (to monitor Gr CVD growth on III-N), Raman spectroscopy (to evaluate the number of Gr layers and defects density), AFM (to investigate the surface roughness of the transferred/grown Gr). Local electrical analyses by CAFM [2] and electrical measurements on properly fabricated test patterns allowed to study the vertical current transport across the Gr/III-N heterostructures. The experimental results were compared with ab-initio DFT calculations of the Gr/III-N interface structure and electronic properties. [1] F. Giannazzo, et al., Phys. Status Solidi A 2016, DOI 10.1002/pssa.201600460 [2] R. Dagher, et al., Phys. Status Solidi A 2017, DOI 10.1002/pssa.201600436

Resume : We studied the features of electron transport in planar GaN/AlGaN heterostructures patterned to nanoribbons (NRs) of different widths. The samples were fabricated by a top-down approach by using MOVPE, e-beam lithography and ion beam etching. Experiments demonstrated that the wide NRs (1110 – 470 nm) have essentially different I-V characteristics in comparison with the narrow NRs (360, 280 nm) that exhibit nonlinear behavior reflecting the space-charge-limited (SCL) current regime at high voltages. For the structure with NRs of 185 nm width the registered current was negligibly small. We explained this width dependence of the electron conductivity by the formation of the depleted zones near the NR edges due to the surface charge traps. We established the effect of the UV excitation on electron transport properties, depending on the wavelength and energy of UV light. We found that the external UV excitation allows to control the edge depletion widths and tune the electron transport, including the SCL regime. These results can be used for developing new NR GaN-based electronic devices. Support of the DAAD, BMBF, and FP7 MCA-IRSES projects is gratefully acknowledged.

Resume : Two types of normally-off GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated by inductively coupled plasma (ICP) and selective area growth (SAG) techniques. The on-resistance, maximum drain current, gate leakage and threshold voltage in SAG GaN MOSFET device are found to be improved significantly compared to ICP device. The defects dependent trapping effects in recessed gate GaN MOSFETs are investigated and the correlation of Vth hysteresis and the lattice damage related traps caused by plasma dry etching process has been confirmed. MOS interface traps density were identified by frequency dependence of conductance technique and shown to be reduced in SAG device. Atomic force microscope (AFM) and X-ray photoelectron spectroscopy (XPS) measurements have been performed to reveal characterization of the semiconductor surface. It show that the step-flow surface morphology was preserved and less nitrogen-vacancy and Ga-O bonds are achieved in damage-free GaN surface in SAG recessed region compared to ICP sample, which are the origin of high quality MOS interface. These results indicate that the SAG technique can provide a powerful method to suppress the interface-related reliability issue. Recently, lots of efforts have been devoted to develop high-performance normally-off GaN-based transistors on silicon substrate. Fully recessed gate GaN metal oxide semiconductor field effect transistors (MOSFETs) is the most promising device schemes where the AlGaN barrier layer in gate region is fully removed and subsequently replaced by insulating oxide dielectric. These devices feature a more positive threshold voltage (Vth) and a larger tolerance in gate swing voltage compared to schottky gate HFETs. Nowadays, it is still ineligible to industry requirement for the recessed gate GaN MOSFET due to its threshold voltage instability. The Vth instability is attributed to electron trapping (or detrapping) in gate region, which may change the potential of the gate, especially presenting a Vth hysteresis window in the double-sweep transfer curves. Therefore, it is extremely important to understand the reason of Vth hysteresis in order to provide technology solutions to minimize these instability issues. Compared with traditional dry-etching recessed gate techniques, selective area growth can achieve recessed gate structure with lattice damage-free GaN surface and control the uniformity of recessed region by regrowth method. In this letter, two types of normally-off recessed-gate MOSFETs were fabricated through ICP and SAG techniques to reveal the correlation of device performance and lattice damage related traps. For the ICP sample, the AlGaN/GaN heterostructure was grown on a 2-inch diameter Si (111) substrate by MOCVD. The total epi-layer thickness is ~1.6 ?m, consisting of a 28-nm AlGaN barrier layer. In the dry-etching process, the AlGaN barrier layer and over 10-nm GaN channel layer were over-etched. For the SAG sample, the structure of GaN-based template was same to ICP one except the gate recess process, in which a 80-nm GaN transition layer, 0.5-nm AlN interlayer (IL), and 28-nm AlGaN barrier layer were regrown selectively to naturally form a recessed-gate structure. For the both samples, the devices were isolated by ICP etching, the gate dielectric layer of 30-nm Al2O3 was deposited at 300 ? by atomic layer deposition (ALD), the source and drain electrodes consisting of Ti/Al/Ni/Au were deposited by e-beam evaporation and annealed at 830 ? for 30 s in N2 ambient, and finally the gate metal Ni/Au was deposited. Transfer curves in linear scale of the SAG and ICP MOSFET were measured at a drain bias of 8 V with Lg/Wg/Lgs/Lgd = 2/100/4/5 ?m. The more positive Vth is achieved for SAG MOSFET compared to ICP MOSFET (2.6 and 1.9 V, respectively). The gate leakage current (Ig) of SAG device shows excellent properties than that of ICP one. Characteristics of the Ig are analyzed by using the correlation of ln(Ig/Vg2) versus 1/Vg. It is well-fitted with Fowler-Nordheim direct tunneling model for the ICP device under high forward voltage. Serial transfer characteristics in semi-log scale of ICP GaN MOSFET and SAG GaN MOSFET were measured with various Vg,max from 4 V to 10 V. The Vth hysteresis (?Vth) versus Vg,max was picked up to evaluate the stability of Vth. The SAG MOSFET shows more stable Vth (small ?Vth) and it is merely 50 mV compared with the large value of 1.05 V for ICP MOSFET at the Vg,max of 10 V. These results indicates that much more traps at MOS interface exist in the ICP device, which would be generated from the damage of GaN lattice under the recessed gate region because of the plasma treatment of dry-etching process. To evaluate the trapping effects of MOS interface, frequency dependence of conductance technique was performed. Measured curves of Gp/? as a function vs ? under different gate voltage in accumulation region for ICP and SAG MOS diode were analyzed. The MOS interface traps density were identified and shown to be reduced in SAG device compared to ICP one (from the range over 1013 to ~ 5×1012-1013 cm?2?eV?1). To reveal the origin of damage related traps, the analyses of GaN surface in recessed region based on AFM and XPS measurements were adopted. The RMS roughness of ICP and SAG sample with a scanned area of 5 × 5 ?m2 is 0.90 and 0.44 nm, respectively. The SAG sample can be maintained in as-grown surface morphology, but the rougher surface in ICP sample do not present as flow-step like surface as SAG one owing to the damage. XPS spectra of N 2s and Ga 3d core-level in GaN surface of recessed gate region for ICP and SAG sample display various components. The N 2s peak intensity decrease for the ICP sample compared to SAG sample, indicating the nitrogen vacancies formed owing to the large plasma damage during dry-etching. The Ga 3d peaks were decomposed into three components, such as Ga-N, Ga-O and Ga-Ga bonds. The much higher ratio of the peak intensity of the Ga-O bonding component to the total Ga3d peak is obtained for ICP sample. The nitrogen vacancies and Ga-O bonding are considered to be the main source of the high-density traps at MOS interface in ICP sample compared to SAG one.

Resume : Recently, high-k dielectrics such as hafnium, zirconium, lanthanum based oxides have been widely researched. they provide decreased Off-state leakage current, high ON-state current and high ON/OFF current ratio. but when high-k gate dielectrics of which band gaps are small are used as gate dielectrics in GaN HEMT, there are large leakage current problems due to small conduction band discontinuity with a AlGaN barrier layer. SiNx by ALD as a interfacial layer can achieve high-quality interface with a low interface state density. but conduction band offset of SiNx / AlGaN interface is lower than that of SiO2/AlGaN or Al2O3/AlGaN. It results in high degree of leakage current of the devices. SiO2 in MOS-HEMT has lower leakage current. but It shows high trapping effect because of its poor interface property in direct contact to the AlGaN barrier layer. SiON is a promising interfacial layer because it has the advantage of both the SiO2 and SiNx. We have fabricated E-mode AlGaN/GaN MIS-HEMT using 5nm SiON / 16nm HfON dual gate dielectrics by atomic layer deposition system. The fabricated devices exhibit low gate and off-state drain leakage current (~10-10and~10-11A/mm, respectively), high on/off ratio(1.2x1011), maximum drain current of 601mA/mm, a threshold voltage of ~1.1V, high field effect channel mobility of 890cm2/V∙s, a breakdown voltage of 810V and excellent dynamic characteristics during switching operation are obtained from Pulse I-V and dynamic Ron measurements.

Resume : In order to exploit the full potential of group-III nitrides for high power electronics efficient electrical insulation of the conducting channel from the substrate/buffer layer structure is mandatory. GaN layers grown by metalorganic vapor phase epitaxy usually exhibit n-type conductivity which severely limits device performance. Additionally, heteroepitaxial growth on lattice-mismatched substrates such as Si may open additional parasitic current paths within the buffer structure. To reduce leakage currents compensation of the background carriers by a deep acceptor like Fe or C is an effective means [1]. Fe shows strong memory effects and its high diffusion coefficient in Si is detrimental for integration of GaN with CMOS technology. Carbon is therefore widely studied to replace Fe as compensating acceptor to realize semi-insulating GaN buffer layers. Commonly the C concentration in GaN layers is controlled by process parameters like reactor pressure, temperature and V/III ratio. We present MOVPE grown layers where high-purity propane is used as C precursor. GaN buffer layers with C concentrations ranging from 1017 to 1019 cm-3 show orders of magnitude decreased leakage currents [2] and high breakdown field strengths up to 1.5 MV/cm . We will present the impact of C doped layers on DC device performance of HEMT devices and compare the structural properties of C and Fe doped GaN. [1] J. L. Lyons et al. , Appl. Phys. Lett. 97, 152108 (2010) [2] A. Lesnik et al. Phys. Stat. Sol. B (2016)

Resume : Recently, vertical nanowire FETs (VNFETs) becomes the promising device technology regardless of its material due to 1) low leakage current due to fully depletion of channel by using wrap-gated structure, and 2) simple and fine control of gate length by using epitaxy growth or metal deposition equipment. In this work, GaN-based Vertical Nanowire FET, which use the undoped GaN channel with the doping concentration of 5ⅹ10^16 cm-3, have fabricated and characterized. First, SiO2 etch mask was deposited. Then nanowire was formed by using E-beam lithography, ICP-RIE etching and TMAH wet etching in sequence to narrow its diameter from 300 nm to 100 nm. Then, etch-back process, which selectively reveal the protruded patterns by coating and etching of resist on the sample, is adapted for deposition or selective etching of ohmic metal or dielectric spacers. The ohmic metallization, gate isolation and pad formation were processed in sequence. The height, channel length and number of nanowire are 1 μm, 300 nm and 27, respectively.The threshold voltage, subthreshold swing, drain induced barrier lowering and output drain current are 0.75 V, 90 mV/dec, 150mV/V and 9 μA, respectively. The on-current through nanowire is bulk current when the gate voltage is close to threshold voltage, so that current was linear to the gate voltage. In addition, the knee voltage is ~ 0.4 V. This is because the doping concentration of channel is as low as 10^16 cm-3, which result in small pinch off voltage.

Resume : InAlGaN/GaN heterostructures have been received increasing interests for high frequency applications due to their high polarization charge density with ultrathin barrier. However, when devices are operated at conditions of high temperature and/or high electrical filed, electrons are trapped and thus the drain current density of the HEMTs is degraded. It is thus desirable to understand the temperature-dependent behaviors of the two dimensional electron gas (2DEG) and related trapping effects, especially in the InAlGaN/GaN with thinner barriers. We investigated the temperature-dependent behaviors of the carrier density in InAlGaN/GaN with different barrier thickness.The 2DEG density of the samples decreases as the temperature increases before temperature turning points, which can be attributed to the shallow trap states in InAlGaN/GaN. After temperature turning points, the 2DEG density increases as the temperature increases. We observed that the temperature turning points increase when the barrier thickness become thinner. In order to figure out the cause of the different temperature turning points, we also investigated the temperature-dependent behaviors of 2DEG in InAlGaN/GaN with SiN passivation layers, and observed that the temperature turning points in these samples are higher than the samples without the passivation layers. We believe that the temperature turning points are related to the surface states. Further investigations are still undergoing.

Resume : High electron mobility transistors based on gallium nitride (GaN) are a key enabling technology to realise high power high efficiency microwave systems and power electronics. GaN-on-Si is highly attractive as a low cost, high performance technology platform. The main drawbacks of Si are the low bandgap and thesubstrate resistive lossy especially at moderate elevated temperatures. The Si sensitivity to Ga unintentional doping during epitaxy causes RF losses, and limited power handling resulting from the relatively low Si thermal conductivity compared to the 4" SiC growth substrate currently used. However the cost benefits are significant allowing 6 inch or even 8 inch wafer with high volume processing. 6" GaN-on-Si epitaxy is already commercially available driven by the emerging GaN-on-Si power switch market, although it is optimised mainly for high voltage switched-mode operation. The use of 3C-SiC interlayer between AlN nucleation layer and Si substrate is a promising alternative to improve the RF power performances and power transistors. This technological process step allow us to reduce the transistor temperature and the GaN/Si substrate losses. The proposed study is conducted to compare a GaN-on-Si structure with and without the 3C-SiC interlayer up to 110 GHz. First results show that the presence of this interlayer process increase the breakdown voltage and the operating frequency of the transistors.

Resume : To address the issue of the relatively low operation voltage of InAlN/GaN HEMTs, we present the fabrication and characterization of AlGaN-channel HEMTs by employing wider bandgap AlGaN instead of conventional GaN channel. In0.17Al0.83N/Al0.05Ga0.95N heterostructures were grown by PMOCVD technique on sapphire and an electron mobility of 511 cm2/Vs was achieved by Hall effect measurement associated with a carrier density of 1.88×1013 cm-2. InAlN/AlGaN HEMTs were fabricated by photolithograph technique with a gate length of 0.5 μm and a gate width of 2×50 μm, a gate-source spacing (LGS) of 0.9 μm, and a gate-drain spacing (LGD) of 2.6 μm. The maximum drain current density was 854 mA/mm at VGS = 2 V with an extrinsic current gain cutoff frequency of 11.6 GHz and a maximum oscillation frequency of 18.9 GHz. A three-terminal breakdown voltage of 87 V was demonstrated at a LGD of 2.6 μm, which is comparable to that of the traditional InAlN/GaN HEMT with similar gate-drain distance reported in the literatures. Furthermore, E-mode InAlN/AlGaN MOS-HEMTs adopting 12 nm Al2O3 insulation layer were also fabricated with the same gate periphery, which exhibited a maximum drain current density of 254 mA/mm at VGS = 5 V and featured a peak transconductance of 116 mS/mm. In addition, a three-terminal breakdown voltage of 141 V was demonstrated at a LGD of 2.6 μm. The obtained characteristics indicate the great potential application of AlGaN-channel device in high voltage electronic devices.

Resume : Polarization engineering opens a way to develop advanced III-N transistor heterostructures. However, it can be difficult to predict the electric field (EF) distribution in a real device as it originates not only from polarization effects but also from residual doping, surface states, etc. In this work contactless electroreflectance spectroscopy has been applied to study the built-in EF in GaN(cap)/AlGaN/GaN Ga-polar heterostructures. A decrease of EF in GaN(cap) layer and an increase of EF in AlGaN layer has been observed with the increase in GaN(cap) thickness. An increase in AlGaN thickness results in a decrease of EF in AlGaN layer and an increase of EF in GaN layer. To determine the distribution of the EF in these heterostructures Schrödinger and Poisson equations are solved in a self-consistent manner and matched with experimental data. It is shown that the experimental built-in EF in GaN(cap) and AlGaN layers does not reach values of field resulting only from polarization effects due to screening of polarization effects by free carriers which are inhomogenously distributed across the heterostructure and accumulate at interfaces [1]. The results clearly prove that combined CER and theoretical studies are able to determine the electric field distribution in III-N heterostructures quantitatively which is important for accurate polarization engineering in this material system. [1] M. Gladysiewicz et al., J. Phys. D: Appl. Phys. 49 (2016) 345106

Resume : Two-dimensional nanowall network (NWN) structure draws a great deal of research attention due to their porous surface nature, continuity in tangential direction and vertical alignment for applications in the area of sensors and other nano-scale devices. In this work, we report the laser molecular beam epitaxy (LMBE) growth and field emission properties of GaN NWN for the first time. The GaN nanowall structures were grown on GaN template and sapphire (0001) substrates by using laser ablation of HVPE grown polycrystalline GaN target in r.f. nitrogen plasma ambient. The growth temperature and pressure conditions were kept in the range of 600~700 C and 2~3E-5 Torr, respectively. The GaN nanowalls are found to be grown as vertically well-aligned network structure with a wall width and porous size of 8-12 nm and 100~200 nm, respectively. The room temperature photoluminescence measurements show a quantum confinement effect in GaN nanowalls with a blue shift of about 90 meV in near band edge emission. From the field emission characteristics, a low turn on field of ~2.5 V/um and a maximum current density of ~0.5 mA/cm2 have been achieved for the LMBE grown GaN NWN structure, which is useful for field emission display applications. The results will be discussed in detail.

Resume : The production of low cost high power electronics has been achieved by the ability to fabricate AlGaN/GaN HEMTs on Si substrates. Due to a CTE mismatch, a transition layer is required to grow a high quality GaN layer. Traditionally an AlGaN/AlN transition layer is used but this forms large tensile strains in the GaN which significantly impacts the device’s performance. Super lattice structures can be implemented to reduce the tensile stress in the GaN and thus reduce the overall amount of defects in the GaN layer. To quantify the overall improvement when implementing a superlattice, a robust and accurate characterization technique is required. Previous literature has shown the monitoring of electrical parameters such as the on-resistance can quantify the amount of degradation the device has incurred. Furthermore, an optical technique known as Electoluminescence has shown to characterize hot electron effects and identify regions of high defect density. In this work, a combination of these characterization techniques is used to assess the effect of the superlattice on device performance and determine whether residual stress impacts the degradation of devices. For the first time, transient electroluminescence measurements, on the microsecond scale, permit the use of this technique when biasing the devices under pulsed conditions. Overall, less degradation and defects are observed in devices with superlattices where a compressive near stress free GaN layer is present.

Resume : We have recently demonstrated an all-GaN integrated cascode with faster switching at 200 V compared to an equivalent GaN E-mode device. Using measured integrated cascode parameters and SPICE simulations, this work addresses known cascode issues, including capacitance mismatch, large oscillations under high current operation and uncontrollable turn-off through the gate resistance, by testing three different integrated source field plate (SFP) configurations. The source field plate (SFP) connected to the source of the cascode or to the floating pad between the E- and D-mode devices places its capacitance, CSFP, in parallel with CGD or CDS of the D-mode device respectively. The switch-on speed for the floating pad connection is faster due to the larger discharging current in the D-mode channel at the expense of a higher potential appearing across the E-mode part, but without the worry of avalanche loss as in the GaN-Si cascode. The third option, with the SFP connected to the gate of the E-mode part acts as an additional Miller feedback capacitor, effectively suppressing dv/dt issues by slowing the device during turn-off and improving controllability. The novel designs are easily achievable in an integrated structure and avoid additional parasitic inductance associated with the equivalent external capacitors required in traditional GaN plus Si cascode devices. This study will form the basis for our future experimental work.

Resume : III-Nitride semiconductors based optoelectronic devices have immense potential owing to their enormous credentials including high thermal stability, high electron saturation velocity, high luminescence, lifetime and excellent thermal/radiation resistance.[1-3] In the present study, we have investigated current transport through a unique structure design which employs high-quality GaN/AlN-based heterostructure with sharp interfaces. A novel approach of structure design has been adopted to understand the current enhancement in heterostructures with a specific number of barrier layers. Such design engineering includes No Barrier Heterostructure (NBH), Single Barrier Heterostructure (SBH) and Double Barrier Heterostructure (DBH) devices having AlN as barrier layers.The high band gap AlN semiconductor offers effective enhancement in current transport through tunneling phenomena. A highly enhanced current transport has been observed in SBH in comparison with NBH and a further improvement is perceived in DBH. This enhancement has been elucidated through a drift-diffusion model in which charge carrier velocity overshoot occurs upon subsequent addition of high band gap barrier layers and resulted in localized high electric field. Furthermore, a UV photodetector has been fabricated using such heterostructure designs with and without AlN barrier layers in metal-semiconductor-metal (MSM) geometry. The MSM geometry offers the benefit of simple fabrication, very low dark currents, high-speed operations, linearity with the optical power and low noise. The UV photodetection device developed using DBH yields photoresponsivity of 102 order higher as compared to NBH device under the illumination of UV light (325 nm). Therefore, the concept of this study is compatible with the general structure of photodetectors as well as solar cells and employment of these structures will enable scaling up the production of highly efficient optoelectronic devices. References: [1] Wu, J., Walukiewicz, W., Yu, K.M., Ager III, J.W., Haller, E.E., Lu, H., Schaff, W.J., Saito, Y., Nanishi, Y. Appl. Phys. Lett., 80, 3967 (2002). [2] Wu, J., Walukiewicz, W., Yu, K.M., Shan, W., Ager III, J.W., Haller, E.E., Lu, H., Schaff, W.J., Metzger, W.K., Kurtz, S. J. Appl. Phys., 94 6477 (2003). [3] Liu, L., Edgar, J.H. Materials Science and Engineering R 37, 61 (2002).

Resume : pn-Junctions are an important building block for vertical power devices. In this study, we report on the first demonstration of pn-junctions fabricated by selective area epitaxy of highly doped p-GaN on patterned n-GaN templates. The n-GaN templates were grown by MOCVD on sapphire and consist of an n+/n structure for quasi-vertical devices, followed by an in-situ deposited SiN mask layer. The templates were patterned using a cyclic ICP dry etching process creating 500 nm deep structures and were treated with TMAH prior to p-GaN regrowth. A highly p-doped GaN with a resistivity of ρ = 0.7 Ωcm was subsequently grown, capped by a thin p++ layer for improved ohmic contact formation. No parasitic GaN growth was found on the SiN mask after regrowth. SEM images of the pn-junction cross section show a sharp interface between the regrown p-GaN and the template in both lateral and vertical direction. An increased V-pit density in the regrown area is observed, which can possibly be minimized by optimizing growth parameters, e.g. by reducing the regrowth temperature. To investigate the electrical characteristic of the pn-junctions, the SiN mask was removed using BOE and p- and n-ohmic contacts were deposited and annealed. IV measurements reveal the rectifying diode characteristics with an on/off ratio of Ion/off = 103 and on-resistance of Ron = 1 mΩcm2. Device performance is most likely limited by surface leakage and not by material or structural quality.

Resume : In this paper we present a new approach for fabricating high-Al AlxGa1-xN pn-junctions over sapphire substrates and demonstrate the use of the same device structure for high-temperature power electronics, UVC emission and solar-blind detection. We employed pulsed MOCVD deposited AlxGa1-xN/AlyGa1-yN short-period-superlattices (SPS) to achieve the individual layer compositions. Our pn-junction device structure consisted of a 3 µm thick high-quality AlN buffer layer, a 0.7 µm thick n-Al0.65Ga0.35N/Al0.75Ga0.25N SPS n-contact formation layer (doping 3x1018 cm-3), followed by a 0.3 µm thick n-Al0.6Ga0.4N/Al0.7Ga0.3N SPS layer (n~ 8x1017 cm-3). The p-side layers included a graded composition Mg-doped AlxGa1-xN layer followed by a p+-GaN contact formation layer. Mesa geometry devices with sizes from 20 to 50 µm diameter were then fabricated with and without surface passivation and characterized at room and elevated temperatures up to 2500C. For a 50µm dia. un-passivated device in reverse bias, a leakage current of 4mA/cm2 and a breakdown field as high as 5 MV/cm was measured. In the forward mode, a turn on at 5 Volts with currents as high as 300 A/cm2 at 10 volts were measured along with a strong light emission at 257 nm (On wafer power~0.3 mW @20 mA). The devices in reverse bias also served as efficient solar-blind UV sensors. The reverse leakage currents and the breakdown fields did not change appreciably with elevated temperatures. In the paper, detailed characterization results for devices with and without surface passivation will be presented.

Resume : Extreme bandgap materials, such as AlN, show promise for ultra high voltage power device applications. By changing the solid Al content of the AlGaN system, the bandgap can be varied between 3.4 eV (GaN) and and 6.2 eV (AlN) with a corresponding shift in the critical electric field from 3.75MV/cm to 10MV/cm. The device structures considered here are circular Schottky contacts to n- Al0.8Ga0.2N on top of n+- Al0.8Ga0.2N. Termination consists of a JTE structure formed by selective removal of a thin magnesium-doped AlN cap layer. Device forward and reverse characteristics were measured as a function of temperature. In addition, for a variety of material and device geometries, the device structures were simulated using a 2D device simulator in order to predict optimum device performance, refine device and termination design, and validate fabricated structures. As-fabricated devices demonstrated a breakdown voltage as high as 500V (with leakage less than 10µA/cm2) but lower than expected. Typical specific on-state resistance was approximately 1 Ohm-cm2 at a current density of about 10A/cm2. Devices exhibited unambiguous rectification including a 6 order of magnitude on-off ratio. This represents the first demonstration of an Al rich rectifier in the AlGaN system. With further material development and device optimization, this system promises high speed, low resistivity unipolar devices operating at higher voltages than current semiconductors.

Resume : Development of GaN on Si devices is critical to reduce the cost of GaN-based power electronics. A method often employed to facilitate high quality growth and engineer the strain state in the GaN layer is to create superlattice (SL) structures that allow for a complete reversal of the state of strain in the GaN from tensile to compressive. The tensile stress in the AlGaN is crucial in forming the 2-DEG, but under pinch-off and operating conditions, the piezoelectric effect can adversely affect device performance and reliability by increasing the strain in the AlGaN, and aiding in the formation of charge trapping locations. In this study, we compare electrical performance degradation of a series of six GaN-on-Si devices, three of which are fabricated using a single transition layer of AlN/AlGaN, and three fabricated with SL transition layers. Using photoluminescence, the GaN residual strain is determined to vary from tensile to compressive between the devices. All devices are subjected to negative gate bias step stressing, and pinch-off forward bias step stressing. Time dependent I-V curves are recorded throughout the tests to determine electrical performance degradation, and Raman spectroscopy is used to investigate the time dependent recovery of the piezoelectric stress, and how it relates to the device recovery time. Additionally, device capacitance is investigated using circuit modeling and the device recovery curves.

Resume : 5 MeV-irradiation with proton of 1E15/cm^2 was performed on AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) with various gate metals of Ni, W, TiN, and TaN to evaluate radiation hardness. Positive shifts of pinch-off voltage and on-current reduction were observed from irradiated HEMTs regardless of type of gate materials. Hall and transmission line measurements confirmed the reduction of carrier mobility and sheet charge concentration due to displacement damage by proton irradiation. Pinch-off voltage shift was dependent on schottky barrier height of gate metal. Gate leakage and capacitance-voltage characteristics did not show any significant degradation demonstrating radiation hardness of schottky contacts.

Resume : In this paper, the effect of a low temperature deposition (100 °C) of an atomic layer deposited ZrO2 gate dielectric on the characteristics of recessed-gate HEMTs on AlGaN/GaN/Si is investigated and compared to those of ZrO2 films deposited at typical ALD process temperatures (250 °C). Conventional MIS-HEMT structures and recessed gate structures with atomic layer deposited-ZrO2 were used for test vehicles to investigate ALD-ZrO2 systematically with regard to their microstructure and electrical properties. The study demonstrates that the leakage current of 100 °C-ZrO2 on GaN is about 2 orders of magnitude lower than that of 250 °C-ZrO2. Moreover, the oxide breakdown voltage on the GaN substrates is higher for the 100 °C-ZrO2 film than for the 250 °C-ZrO2 film. This result opposes the finding for the same study performed on Si substrates due to the lower impurity level and higher film density for dielectric films on Si. In contrast to the leakage current characteristics on the Si substrate, the low temperature atomic layer deposition process on GaN substrates exhibits a reduction of leakage current, hysteresis, and Dit while improving the pulse characteristics. This report presents a detailed analysis of the electrical behavior, interfacial layer effect and dielectric properties for this promising approach to gate dielectrics for recessed gate GaN HEMTs. Acknowledgement: This work was supported by the Future Semiconductor Device Technology Development Program (Grant 10045216) and funded by the IT R&D program of MOTIE/KEIT (Grant 10048933). We thank TMEIC for providing the ozone generator used in this work. This work was supported by the Postdoctoral Research Program of Sungkyunkwan University (2015).

Resume : In this work, AlGaN/GaN MIS-HEMTs with 15 nm thick SiNx gate dielectric deposited by hollow cathode plasma-enhanced ALD were investigated. The ID–VG transfer characteristics demonstrated excellent threshold voltage (Vth) stability and a small hysteresis (~100 mV) under a large forward gate bias (VG,max =10 V). Similarly, the capacitance-voltage (C–V) characteristics showed negligible Vth shift and hysteresis with increasing the maximum gate bias VG,max up to 10 V. Furthermore, the first peak in the conductance-voltage (G–V) curve, which indicates the formation of 2DEG channel at the barrier/GaN interface, exhibited similar behavior. Interestingly, the second peak in the G–V curve, an indicator of electron spillover to the dielectric/III–N interface, was absent. In contrast, the ALD Al2O3 MIS-HEMTs sample showed a large Vth shift and hysteresis in the ID–VG, C–V, and G–V characteristics, while both peaks in the G-V curve were clearly present. Furthermore, the PEALD SiNx MIS-HEMTs (LSG/LG/LGD=4.5/5/6.5 µm, VDS=10 V) showed a high on/off ratio 109, a steep subthreshold swing of 72 mV/dec and a maximum drain current ~550 mA/mm. PEALD SiNx also showed excellent film properties (e.g., high refractive index 2.0, high density 2.9 g/cm3, and high breakdown electric field ~11 MV/cm). Acknowledgement: This work was supported by the Future Semiconductor Device Technology Development Program (#10045216) and the IT R&D program (#10048933) of MOTIE/KEIT, Korea.

Resume : Recently, LED Filament lamps have been emerging as a generic product category in the market, without compromising on optical properties, form factor or volume capabilities. The key advantage of the filament is that the LEDs be configured for omnidirectional light which has been lacking in most commercial LED lamps adopting surface-mounted of chips. Despite the domestic demand for the LED filament light bulbs is growing rapidly, some of their features are still found to be less satisfied than conventional incandescent bulb, in terms of visual discomfort and emission uniformity. The most common solution is to adapt external optical components, such as lenses, and diffusers, which results in poor optical coupling efficiencies and absorption loss. It has been proved that elongated geometrical shaping of LED chip can increase luminescence efficiency, as well as decrease luminous exitance by distributing radiation evenly along the longitudinal direction [OE, 23, 15021-15028 (2015)]. In this work, we fabricate a 15-cm-long LED tube by mounting the 15 elongated LED stripes onto an aluminum PCB in flip-chip bonding. Such flip-chip bonding process improves both the light extraction efficiency and current spreading. High thermal conductivity of aluminum PCB further reduce bulky electronic components as a heat sink.

Resume : The drain delay becomes a main frequency limitation of GaN HEMT when the gate length of is decreased under 100 nm. The drain delay is the transit time in the drain depletion region, which is caused by the vertical electric field component of Vds. In this work an AlN passivation layer is proposed to suppress the drain depletion and reduce the drain delay. Due to the piezoelectric polarization effect between the AlN layer and barrier layer, a fixed positive charge layer with high concentration (~1014/cm2) is formed at the interface. This fixed positive charge layer produces a converse vertical electric field, which can compensate the vertical component of Vds. Therefore, the drain depletion is suppressed by the AlN passivation layer. Moreover, because the piezoelectric polarization charge is fixed charge, it wouldn’t introduce additional parasitic capacitance. Simulations were conducted on a GaN HEMT with 20nm gate length to improve this method by Synopsys Sentaurus. The spontaneous polarization and piezoelectric polarization physical models are used in every heterojunctions of the simulated device. The Vds is 7V and Vgs is -1V in the simulation to mimic the work condition in class-A amplifier. According to the simulation results, the traditional HEMT exhibits a 30nm wide depletion region while the optimized HEMT nearly has no depletion region. S-parameter simulations were also conducted, which indicates that the fmax is increased form 241 GHz to 293 GHz. The Simulation results indicate that the AlN passivation can obviously reduce the drain delay and increase the device work frequency.

Resume : We have demonstrated lateral 1-D nanowire transistor controlled by a non-contacting side gate with air as dielectric. The nanowire is fabricated on AlGaN/GaN heterostructure by a top down approach using a combination of dry and anisotropic wet etching. The nanowires are site-controlled with high aspect ratio (20 µm/10 nm), thickness controllable and discrete. The gate is lithographically defined parallel to the nanowire on either sides and is electrostatically coupled to the channel from three sides similar to the ?-gate. The effective control can be increased by placing the gate closer to the channel, increasing the height of the metal stack and a dielectric encapsulation of nanowire. Room temperature quantum effects is observed since the channel can be narrowed down to less than 10 nm so as inter sub-band separation becomes more than the thermal energy. The transfer characteristics shows rise in current with interleaved plateaus as the gate voltage changes. Oscillations are observed in the transconductance which is attributed to the quantum capacitance which dominates over geometric capacitance in 1-D systems. The output characteristic shows a non-linear and non-square law dependence of the saturation current with the gate voltage typical of a 1-D transistor. The gate leakage is found in pico-ampere (pA) range for positive gate bias and sub-threshold slope of 125 mV/decade is observed.

Resume : Recently, gallium oxide (Ga2O3) has gained great attention as a new semiconductor candidate for future power electronics. In addition to the availability of affordable native substrates produced from melt-grown bulk single crystals, Ga2O3 has some other great attributes: a bandgap of 4.5 eV leading to a large breakdown electric field of 7~8 MV/cm, good controllability of electron densities over a wide range of 1e15~1e20 cm-3 through intentional donor doping, and Baliga's figure of merit several times larger than those for GaN and SiC. However, Ga2O3 electronic devices are still at a primitive stage of research and development and thus remain far less mature than the ones based on GaN and SiC. We have been pursuing pioneering developments of Ga2O3 transistors and diodes, and significant progress has been made in the last several years. In this talk, we will give an overview of Ga2O3 technologies developed for power switching device applications. State-of-the-art Ga2O3 MOSFETs with a gate-connected field plate showed an off-state breakdown voltage of 755 V, a large drain current on/off ratio of over nine orders of magnitude, DC-RF dispersion-free output characteristics, and stable high temperature operation up to 300°C. Vertical Ga2O3 Schottky barrier diodes with a net donor concentration of 1.8e16 cm-3 exhibited a specific on-resistance of 5.1 mΩ·cm2, an ideality factor of 1.05, and a breakdown voltage of 1076 V.

Resume : Although GaN-based enhancement-mode (E-mode) discrete power HEMTs using p-GaN gate technology are already commercially available and offer superior performance over the mainstream Si power transistors, the indispensable peripheral logic control circuitry is still implemented with a separate Si CMOS IC. Compared to fully integrated solutions, such a hybrid scheme usually features larger parasitic inductances that inevitably limit the performance of GaN power switches. Hence, in order to fully exploit the advantages of GaN power devices, it is of significant importance to develop GaN-based mixed-signal ICs monolithically integrated with GaN power transistors for an ultimate system-on-chip GaN smart power solution. In this work, monolithic integration of 0.5-μm E/D-mode (enhancement/depletion-mode) HEMTs was demonstrated on a p-GaN gate power transistor platform. The E-mode HEMTs feature p-GaN gate, while the D-mode HEMTs feature Schottky gates under which the p-GaN layer is completely removed. At room temperature, the threshold voltage is -1.33 V for the D-mode HEMT and +1.6 V for the E-mode HEMT. The maximum drain current density is 456 mA/mm (at VGS = 1 V) for the D-mode HEMT and 336 mA/mm (at VGS = 6 V) for the E-mode HEMT. A DCFL (direct-coupled FET logic) inverter and a 101-stage ring oscillator (RO) featuring E/D-mode HEMTs were fabricated and characterized at a supply voltage VDD = 5 V. For the inverter, the output high (VOH) and low (VOL) voltage of the inverter are 5.0 V and 0.33 V, respectively, corresponding to an output voltage swing of 4.67 V. The oscillation frequency fosc of the RO is 43.7 MHz, yielding a propagation delay tpd of 113.3-ps. To prove the feasibility and high performance of GaN-based logic ICs, a D flip-flop (DFF) which is widely used in logic circuit applications was demonstrated. The DFF consists of one inverter and four NAND gates in the circuit, featuring data and clock signal terminals as input ports. The extracted rise time and fall time at the output terminal are only 2.8 ns and 1.6 ns respectively, with a clock frequency of 2-MHz. All the logic ICs demonstrated in this work operate properly from room temperature to 250 degree Celsius, suggesting their seamless compatibility with the p-GaN gate power devices.

Resume : In this work, we demonstrate the excellent high temperature performances of the depletion-mode AlGaN/GaN/AlGaN double heterostructure (DH) and AlGaN channel HEMTs (AlGaN-based HEMTs). The single heterostructure (SH) HEMTs and DH HEMTs with high electron mobility of 1777 cm2/Vs, 1604 cm2/Vs at room temperature and 541 cm2/Vs, 616 cm2/Vs at 573K high temperature was obtained, respectively. The mobility of AlGaN-based HEMTs is less sensitive to changes in temperature. AlGaN-based HEMTs exhibit superior transport characteristics in comparison to traditional HEMTs with AlGaN/GaN single heterostructure at high temperatures. As temperature increases from room temperature to 573 K, the saturation drain currents of DH HEMTs and AlGaN channel HEMTs are reduced by 38% and 20%, respectively. However, the saturation drain current of SH HEMTs is severely reduced by 51% as temperature rises to 573 K. Meanwhile, the high temperature breakdown characteristics of AlGaN-based HEMTs are significantly improved compared to that of conventional AlGaN/GaN HEMTs. Then, we combine these heterostructures with the p-gate technology. The combination not only increases the breakdown voltage and threshold voltage but also improves the high temperature performances of enhancement-mode AlGaN-based HEMTs. Therefore, AlGaN-based HEMTs are more suitable for the applications in high temperature electronic devices.

Resume : AlGaN/GaN HEMTs and Schottky barrier diodes (SBDs) on silicon substrates are very promising for future efficient, low-cost and compact power applications. Nanoscale technologies, such as tri-gates, offer superior channel control and large reduction in off-state leakage current (Ioff), at the expense of degraded on-state performance due to the removal of a portion of the 2DEG during nanowire etching. Moreover, current tri-gate HEMTs and other nanowire-based devices exhibit much lower breakdown voltage (Vbr) than planar devices. This talk will cover nanoscale technologies that significantly enhanced the performance of high-voltage GaN HEMTs and SBDs. The degradation due to partial removal of carriers in the tri-gate region was completely eliminated by optimizing the tri-gate geometry, which resulted in large on/off-current ratio with a similar drain current and on-resistance (Ron) of the reference planar HEMT. The Vbr was significantly increased, by up to ~500 V, with an integrated field plate. With a gate-to-drain separation (LGD) of 5 μm, the tri-gate HEMT presented high Vbr of 792 V at 0.3 μA/mm along with very small Ron of 0.91 mΩ·cm2. Optimized tri-gate HEMT with LGD of 10 μm resulted in hard Vbr of 1755 V at 45 μA/mm with high soft Vbr of 1350 V at 1 μA/mm, rendering state-of-the-art figure of merit (FOM) up to 1.2 GW/cm2. In addition, a hybrid of tri-anode and tri-gate architecture was developed for SBDs exhibiting high Vbr, ultra-low Ioff and small turn-on voltage (~0.75V) since the tri-anode forms direct Schottky contact to the 2DEG. The reverse characteristics are controlled electrostatically by an embedded tri-gate transistor, instead of relying only on the Schottky barrier, which resulted in ultra-low Ioff below 10 nA/mm at large reverse biases up to 500 V. These devices exhibited record Vbr up to 1325 V at 1 μA/mm, rendering an excellent FOM of 939 MW/cm2. These results reveal the outstanding potential of nanowire approaches for high-voltage and low-leakage GaN power devices.

Resume : Vertical GaN transistors have been explored recently as an alternative to their lateral counterparts for power applications, since increasing the breakdown voltage does not require that the chip area increase. Vertical designs with minimal chip area have been demonstrated, using a double gated fin to control the current flow with sub-micron dimensions. Most previous demonstrations have utilized difficult to reproduce or transfer techniques to fabricate the transistors, such as planarization and etch-back, and e-beam lithography. In order to simplify the process and improve transferability and manufacturability, a fully self-aligned process has been developed that avoids the use of such difficult steps. Optical lithography using an i-line stepper system is used to define fins as small as 300 nm. The hard mask stack used for the fin formation etch is specially composed to give a clean transfer of the pattern to the GaN, leave a source metal in contact with the source n+ regions, and ensure that the GaN surface is minimally affected to result in smooth etched surfaces. An ALD oxide and gate metal is used to guarantee conformal sidewall coverage of the gate on the fin. Devices were patterned as individual fins as well as small sets of fins with varying dimensions and spacing in order to compare the effect various design parameters on the characteristics. A threshold voltage of -7 V, was measured, with an Id of 5 kA/cm^2 at 3 V, limited by the schottky nature of the contacts.

Resume : The linearity of GaN transistors ultimately limits their performance in many applications, especially for device with very short gate. Our group has previously developed a Fin-like nanowire-channel structure and improved the device linearity significantly [1]. In contrast to the planar GaN HEMTs, the gm and fT drop is very small at higher gate bias Vg >1 V. However, the gate Leakage current Ig of this device increases very fast at positive Vg which in turn prevents the device from operating at high gate bias. In this work, we introduce a thin layer of oxide between the metal gate and the InAlN barrier in order to reduce the Ig and increase the gate voltage and drain current swing. An 80 nm-gate Al2O3/InAlN/GaN Fin-like nanowire-channel MISHEMT was fabricated on a Si substrate and its DC/RF characteristics were measured. The device fabrication process follows the same as that reported in [1] except that a 6-nm Al2O3 gate dielectric is inserted by ALD deposition before gate formation. At Vg=3 V, the Ig is 2.4 x 10-7 mA/mm for the Fin-like nanowire-channel GaN MISHEMT whereas the Ig of a typical Schottky-gate GaN HEMT reaches 1 mA/mm at Vg =1.2 V [1]. The fabricated device shows higher current drivability (>1.8A/mm compared with 1.5 A/mm of planar GaN HEMT) and four times higher (6.5 V to 1.3 V) gate voltage swing (GVS) value (which is defined as the range of Vg that the fT remains not smaller than 80% of its peak value) compared with planar GaN HEMT [1]. This allows the Fin-like nanowire-channel GaN MISHEMT to be able to operate at even higher gate voltage (>3V) with good linearity performance. [1] W. C. Xing, et. al. EDL, submitted.

Resume : GaN-based transistors are attractive for the high power and high frequency device application due to their superior material properties. However, the current collapse is one of the critical issues which severely degrades the device performances. In this work, we fabricated and characterized the AlGaN/GaN nanowire gate-all-around (GAA) FETs using GaN-on-insulator (GaNOI) wafer. The 25 nm-thick Al0.25Ga0.75N barrier layer was grown on the GaNOI wafer to form the AlGaN/GaN heterostructure. For device fabrication, the AlGaN/GaN nanowires were defined by e-beam lithography and etched by RIE and followed with TMAH wet treatment. The GAA structure was obtained by completely removing buried SiO2 layer under the AlGaN/GaN nanowires. 25 nm-thick Al2O3 gate insulator and 20 nm-thick TiN gate metal were then deposited by atomic layer deposition. After contact hole opening for the source and drain, Ti/Al/Ni/Au was deposited. For comparing, the planar device was fabricated on same wafer with gate width of 27 um. The pulse mode characteristics for the AlGaN/GaN nanowire GAA FET exhibited the current collapse free operation while the planar AlGaN/GaN device suffers from severe gate and drain lag. The proposed nanowire device exhibited excellent on- and off-state performances, such as off-state leakage current of 1E-11 A, Ion/Ioff ratio of 1E+7, maximum drain current of 0.7 mA, and threshold voltage of -4 V compared to those of the planar device structure (Ioff = 1E-7 A, Ion/Ioff = 1E+2, IDS, max of 1.2 mA, and Vth of -7 V). These enhanced device performances are because the nanowire structure is almost buffer-less and the channel becomes fully depleted at off-state due to the wrapped gate configuration.

Resume : For the last two decades resonant tunneling transport of electrons has remained largely elusive in III- Nitride semiconductor quantum heterostructures. The root cause has been attributed to the presence of defects thus charge trapping, particularly dislocations in heterostructures grown on GaN on foreign substrates, i.e. heteroepitaxy. Under an ONR MURI project, in 2015 we succeeded for the first time in growing and demonstrating AlN/GaN resonant tunnel diodes (RTDs) on bulk GaN substrates that reliably oscillates at room temperature and cryogenic temperature, which indicates the defect level has been controlled to be sufficiently low. These results were subsequently reproduced by the other MURI team members as well. Our theoretical and experimental studies of these III-Nitride RTDs reveal [arXiv:1606.08100] that the quantum transport in these devices exhibit features that are unexplainable using existing semiconductor theory. The robust resonant transport, characteristic of these devices, has enabled us to track these features to the broken inversion symmetry, which generates built-in spontaneous and piezoelectric polarization fields. Interestingly, these RTDs also emit UV light with an intensity tracks with the current density. We currently believe holes are induced by impact ionization in the collector region, subsequently leading to light emission. ACKNOWLEDGEMENT: support is gratefully acknowledged from ONR and NSF.

Resume : Resonant tunneling transport of electrons in III-Nitride quantum heterostructures has been studied during the last two decades with limited success. Recently we have demonstrated repeatable room temperature negative differential resistance in double barrier GaN/AlN resonant tunneling diodes (RTDs) with peak current densities of 6.4 kA/cm^2. In the present work, we report for the first time III-Nitride RTDs exhibiting a record high peak current density. The device structures were grown by molecular beam epitaxy (MBE) on the c-plane of commercially available n-type single-crystal GaN substrates. Si-doped n-GaN layers were grown as contact regions and un-intentionally doped spacers were introduced to minimize dopant diffusion into the quantum well. The active region comprises two 1.5 nm-thick AlN barriers confining the bound-states of a 1.5 nm-thick GaN quantum well. Room temperature current-voltage characteristics reveal a typical peak current density of 183 kA/cm^2 under forward bias. The typical valley current was measured at 150 kA/cm^2 with a peak to valley current ratio of 1.2. To guide our design of high current density III-Nitride RTDs, an electrostatic model has been developed, which accounts for the spontaneous and piezoelectric polarization fields. Analytic expressions for the peak current density and peak voltage, which capture the unique effects of polarization fields on resonant transport, have been derived showing a good agreement with our experimental results.

Resume : Most studies of group III-N-based electronic devices so far have been focused on heterostructures grown in the cation-polar direction. The opposite direction of polarization, i.e., N-polar direction, can also be employed in growth for unique device properties. In addition, the N-polar direction has its own advantage in epitaxial growth due to the polarity dependent decomposition temperatures of the materials, eventually enabling the N-polar materials to be grown at much higher temperatures than the cation-polar counterparts. However, the N-face orientation has received less attention due to difficulties in high-quality growth mainly due to defective substrates. In this work, using N-polar single crystal Ammono GaN bulk wafers with high structural perfection and atomically flat surfaces, we demonstrate the homoepitaxy of high-quality N-polar GaN p-n diodes by molecular beam epitaxy (MBE). The N-polarity of a grown GaN p-n diode was confirmed from a Ga-rich surface reconstruction. Although clear atomic steps are observed on the surface of the N-polar GaN p-n diode, overall step meandering manifests during the step-flow growth. The diode was grown with Si-doping for n-GaN, and Mg-doping for p-GaN. The fabricated p-n diodes have a forward turn-on voltage of ~3.5 V and an on/off current ratio of 10^9 at ±5 V. This is the highest quality p-n diode ever demonstrated on the N-polar GaN epitaxy. The built-in potential of the device was estimated to be ~3 V from the junction capacitance vs voltage measurements. Under current injection, room temperature electroluminescence spectrum was observed, dominated by band-to-band and Mg acceptor-related luminescence peaks, while deep level-associated yellow luminescence band is seen to be weak.

Resume : Controlling the GaN surface and high temperature instability are the primary challenges impeding GaN power Schottky diodes and relegating high power electronics to GaN p-n junctions. In this work, we demonstrate overall stability of GaN Schottky contacts with a report on defect-free homogeneous behavior of Ni Schottky contacts patterned on surface treated n-GaN by photolithography with unity ideality factor, high temperature stability, and low reverse leakage. The barrier height (0.7 eV) and ideality factor (<1.02) are found to be independent of temperature, indicating a highly homogeneous contact. The contacts are found to be stable with no significant change in ideality factor or leakage current up to an annealing temperature of 600°C. Temperature dependence of the reverse leakage current shows no evidence for the existence of surface defects that would provide leakage paths and the behavior was modeled by an ideal homogeneous barrier of 0.7 eV. Consequently, the forward and reverse bias characteristics were explained by the same single homogenous Schottky diode. The surface treatment after the development and prior to metallization included an acid-based chemical treatment. XPS studies indicate that the hydroxide-based development process during photolithography changes the nitride surface composition by introducing excess C that degrades the ideality factor and introduces barrier inhomogeneity, thermal instability and high leakage currents. XPS studies further demonstrate that the restoration of a stable, Ga-rich surface, similar to as-grown surface, occurs due to the acid-based surface treatment, which is responsible for the observed unity ideality factor, homogeneous barrier, low leakage current, and high temperature stability.

Resume : Vertical GaN Junction Barrier Schottky (JBS) Diode fabricated by selective area p-GaN regrowth are demonstrated. JBS Diode has a structure in which p-type layers are arranged with a few microns in between, in the surface of n-type layer. Because the p-GaN formation by ion implantation is known to be technically difficult, we developed a method for the selective area p-GaN regrowth In this presentation, I will introduce about the difficulty of the p-GaN selective area regrowth and demonstrate the GaN vertical JBS Diode with ideal forward property. We used SiO2 as a mask material. In the case of H2 carrier growth, the growth rate in a small trench was a few times higher than that on the planer surface, and p-GaN grew abnormally. In the case of N2 carrier growth, the growth rate in the trench was similar to the planer growth. However, SiO2 mask was hardly removed by HF cleaning after the regrowth because GaN was deposited on SiO2. In addition, there was a ridge structure between regrown p-GaN and N-GaN. Low pressure growth makes the height and width of the ridge lower. The leakage of the PN Diode fabricated by the selective area p-GaN regrowth was significantly high. SiO2 mask may be decomposed during regrowth. Finally, JBS Diode fabricated by selective area p-GaN regrowth was demonstrated. The threshold voltage was at around 0.8 V (Schottky Barrier) and the on-resistance was 2~3 mohmcm2 and the on-resistance was decreased to less than 1 mohmcm2 at around 3.5V (Turn-on voltage of PN Diode).

Resume : Temperature dependence of barrier heights of Ni/n-GaN Schottky barrier diodes fabricated on a MOVPE-grown GaN homoepitaxial layer were investigated in detail by using capacitance-voltage (C-V) and forward current-voltage (I-V) measurements in the range of 223-573 K. The barrier height obtained from C-V characteristics decreased with increasing temperature with the temperature coefficient of -1.7×10^(-4) eV/K. On the other hand, the barrier height obtained from the I-V analysis based on thermionic emission (TE) model increased with increasing temperature. We performed numerical calculations of simple TE and thermionic emission-diffusion (TED) models and found that a decrease in electron mobility with increasing temperature has strong impact on the barrier height estimation, i.e., simple TE analysis results in overestimation of barrier heights at elevated temperature. Therefore, we obtained the barrier height by numerical fitting of the TED model with temperature dependence of electron mobility. The obtained barrier height shows negative temperature dependence with the coefficient of -2.3×10^(-4) eV/K, which shows good agreement with that obtained from C-V measurements. To the best of our knowledge, this is the first consistent report on the temperature coefficient of barrier height in GaN. The coefficient is about half of the temperature coefficient of band gap reported previously, indicating that the decrease in the barrier height may originate from shrinkage of band gap.

Resume : Longitudinal elastic and piezoelectric properties of single crystal aluminum nitride (AlN) films will be reported and resulting Bulk Acoustic Wave (BAW) device performance above 3 GHz will be discussed. Films were grown via Metalorganic chemical vapor deposition (MOCVD) on 150-mm diameter c-plane silicon carbide (SiC) substrates. Dramatic improvements in d33 were measured on wafer resulting in improved e33 being extracted. These parameters suggest that resonators based on single crystal material are capable of electromechanical coupling coefficients, kt2, up to 9.5% and k2eff in excess of 10%. These results are driven by enhancements in material quality resulting in improved elastic and piezoelectric properties demonstrating the advantage of single crystal AlN films over their polycrystalline counterparts for high performance BAW filters. Emerging 5G, Wi-Fi and 4G LTE communication standards require compact, low loss, wide bandwidth filters with steep skirts in mobile and fixed communication devices. The center frequencies of interest for these communication standards extend from traditional bands (below 2.6 GHz) to newer LTE frequency bands at 3.4-3.8 GHz, emerging 5G bands in 3.3-4.2 GHz range as well as WiFi between 5 and 6 GHz. RF filters for mobile communication devices utilize acoustic resonators which are based on surface acoustic waves (SAW) or longitudinal bulk acoustic waves (BAW). At these higher frequencies, SAW filters require smaller width and pitch of the interdigitated transducers, thus limiting performance, therefore BAW is the primary technology in use above 2.5 GHz. Film bulk acoustic resonators (FBAR) and solidly mounted resonators (SMR) are the dominant technologies currently utilized in BAW RF filters due to their small footprint, high Q-factor, high operating frequency, and good power handling. Traditional FBAR and SMR BAW resonators are constructed using polycrystalline thin film piezoelectric AlN materials deposited via physical vapor deposition (PVD) on <111> silicon substrates. A critical parameter for RF filter design is bandwidth, which is primarily driven by the electromechanical coupling coefficient, kt2 , of the piezoelectric materials selected. A limiting property of current PVD-AlN based resonators is their low kt2 (e.g. 6.5-7.0 %), which arises due to lower than desired piezoelectric properties of the films. While this kt2 value is adequate for historical frequency bands, the higher frequency bands noted above are more challenging with respect to bandwidth creating a strong demand for higher kt2 piezoelectric materials. Recent studies have demonstrated that the piezoelectric coefficient, e33, (and subsequently filter bandwidth) of PVD-AlN films can be increased by alloying with scandium (Sc) or co-doping of AlN using Mg-Zr or Mg-Hf, however the improvement in bandwidth is typically accompanied by a decrease in Q-factor resulting in only marginal performance improvements. In contrast, the AlN films used in this work are epitaxially grown by MOCVD on SiC, which is an ideal RF substrate platform for high performance at high frequency due to its low loss and excellent thermal conductivity. In addition, SiC substrate technology has matured to commercial availability and use of semi-insulating (SI) 6-in SiC and 8-in SI SiC in development. Single crystal AlN films grown by MOCVD on SiC substrates have inherently higher crystal quality compared to polycrystalline PVD AlN, as evidenced by (004) X-ray diffraction (XRD) rocking curve FWHM of 0.025◦, compared to typical FWHM of 2-3◦ in PVD AlN. The superior crystal quality also translates to improvements in the piezoelectric properties of the film. While early work has been published on epitaxial III-N films for acoustic resonators, the results may have been limited by the fabrication processes or material.

Resume : Compact devices with unique switching performance, this has been the promise of GaN power devices since several years. And now we are experiencing the exciting time when this is becoming reality. Advanced GaN technologies will be a decisive step towards energy efficiency and size & weight reduction in a variety of applications which today are still dominated by silicon devices. This plenary talk will provide a technology performance comparison between GaN and Si power devices and will try to answer the question where GaN will succeed. The development and implementation of benchmark GaN-on-Si enhancement mode power technology in a high-volume Si manufacturing line leading to Europe’s most comprehensive power device fab will be presented. A key success factor is an outstanding R&D eco-system which will be highlighted by sharing our contribution to the European funding project PowerBase in which 39 partners throughout the entire value chain, ranging from base-material to final application, teamed up to pioneer the path for a wide adoption of GaN power technology in a broad application spectrum. First successful uses of 600V enhancement mode GaN products in high performance applications will be shown. Examples will include highest efficiency high power switched mode power supplies for server and telecom applications as well as high frequency DCDC stages resulting in unique increase of power density and reduction of form factor.