Material and device integration on silicon for advanced applications

Resume : The integration of semiconductors (SCs) and magnetic materials offers a promising route to develop the next generation of energy-efficient information technology and go beyond CMOS. The spin-MOSFET, whose source and drain are ferromagnetic, is one the key devices in SC spintronics. Its operation is based on the injection, transport and detection of spin-polarized carriers in a lateral SC channel. Silicon, owing to its compatibility with the existing CMOS technology and its long spin coherence, is the most suitable candidate to develop spin-based SC devices. Although the electrical injection, transport and detection of spins in silicon have been achieved, the induced spin accumulation was much smaller than expected and desired, limiting the potential impact of Si-based spintronics devices. Here, we have fabricated Si lateral devices with Fe/MgO magnetic tunnel contacts and demonstrated efficient spin injection, transport and detection in a Si channel up to room temperature. Non-local spin-valve and Hanle measurements performed at various biases and temperatures indicate that the tunnel spin polarization of Fe/MgO reaches 53 % at 10 K, which is the highest value reported to date. We also show that we can significantly enhance the spin accumulation in Si by designing a spin injector with a width comparable to or larger than the spin-diffusion length in the Si. The experimental data are in excellent agreement with numerical calculations that are based on the standard theory for spin injection and diffusion in a non-magnetic material. From our results, we deduce that a spin accumulation of more than 10 meV is present in the Si channel at 10 K, proving that large carrier spin polarization can be created in Si-based spintronics devices.

Resume : The availability of integrated light sources is the key technology for the whole Si photonics industry. The direct epitaxial growth of III-V lasers on Si-photonics circuits appears as the most promising, cost-effective and versatile approach. III V heteroepitaxy on Si has for long proven difficult due to the conjunction of large lattice-, thermal- and polarity- mismatches. However, much progress has been made in the recent years on the understanding and mastering of these issues. The first issue to deal with when growing III-Vs on Si is the substrate preparation. Indeed, III-V epitaxial reactors are generally not adapted to in situ Si de-oxidation which requires very high temperatures and clean environment. The lattice mismatch between GaSb and Si is as huge as ~13%. The nucleation process is thus of uppermost importance. Inserting a thin AlSb nucleation layer, the thickness of which depends on the growth temperature, results in the best material quality and X-ray rocking curves linewidth comparable to that of GaAs or Ge on Si (mismatch ~ 4 %) are achieved. Transmission electron microscopy (TEM) investigations reveal the formation of a network of interfacial misfit dislocations which very efficiently relieve the strain, together with micro-twins and antiphase domain boundaries. Continuous-wave lasing has been achieved above room-temperature between 1.5 and 2.X µm with GaIn(As)Sb/AlGaAsSb laser diodes grown on such buffer layers. Work partly supported by the French ANR (project OPTOSi, ANR-12-BS03-002 and project ANTIPODE, ANR-14-CE26-0014) and program on "Investments for the Future" (EquipEx EXTRA, ANR-11-EQPX-0016).

Resume : Silicon photonics now matured as a CMOS compatible technology for high-speed optical communication. Active electro-optical switches and modulators are key components of such integrated optical circuits. For long-haul communication, such components typically rely on the linear electro optical effect in bulk lithium niobate. Contrary, such effect cannot be exploited in silicon photonics due to the absence of the Pockels-effect. In our work, we will discuss the co-integration of silicon photonics with novel, nonlinear-optical materials for active electro-optical devices. We focus on barium titanate (BTO) epitaxially deposited on silicon substrates [1] and show the influence of the BTO materials properties such as porosity on the electro-optical performance [2]. Successively, we will present a BTO/Si-waveguide platform with passive and active devices, such as waveguides with low losses of <6 dB/cm [3], resonators with quality factors of >20’000, active switches with low-power tunability of 4 W/nm [4] and high-speed electro-optical modulators. Finally, we will discuss the prospects of the BTO/Si waveguide technology for applications beyond optical communication, such as photonic neuronal networks for pattern recognition. [1] S. Abel et al. Nat. Commun., vol. 4, p. 1671, 2013. [2] K. J. Kormondy et al. Nanotechnology, vol. 28, p. 75706, 2017. [3] F. Eltes et al. ACS Photonics, vol. 3, p. 1698, 2016. [4] S. Abel et al. J. Light. Technol., vol. 34, no. 8, pp. 1688–1693, Apr. 2016.

Resume : III-V semiconductor nanowires (NWs) are promising candidates for the next generation of optoelectronic devices due to their unique properties such as enhanced light absorption. The axial relaxation of the strain allows the combination of lattice mismatched materials like GaAs and Si. In most practical cases, the absorption in the nanowires is challenging to measure because NWs are fabricated on opaque substrates. The possibility of estimating the absorption from the reflectance has been proven [1], showing the interest in this optical characterization. In this work, series of samples consisting on self-catalyzed GaAs NWs on Si(111) were grown by Molecular Beam Epitaxy following the Vapor-Liquid-Solid mechanism. We changed the growth temperature in an interval between 555 and 630 ºC as well as the thickness of the oxide layer of the substrate. As a consequence, we found a dependence of the geometrical characteristics of the NWs with the growth conditions. We have measured the reflectivity and correlated it with the dimensions, density and proportion of vertically oriented NWs. Finally, the experimental values were compared with those obtained by theoretical calculations [1,2] and were supported by an in-depth SEM analysis. [1] N. Anttu et al., Opt. Lett., 38, 1449-1451 (2013) [2] R.A. Street et al., Nano Lett., 9 (10), 3494-3497 (2009)

Resume : The epitaxy of high Sn content (i.e. 16% and 13%) GeSn alloys in a 200 mm industrial Reduced Pressure - Chemical Vapor Deposition tool has been investigated. A specific Step-Graded approach has been set up to grow thick, high Sn content GeSn layers on Ge buffers, themselves on Si (001) substrates. The benefit of this step graded approach, in terms of crystalline quality and surface morphology, has been demonstrated using X-Ray Diffraction, Atomic Force Microscopy and Transmission Electron Microscopy. A gradual relaxation of the built-in compressive strain occurred in the grading (Macroscopic Degree of Strain Relaxation R ~ 70% in the top layers), minimizing Sn segregation and precipitation. Photoluminescence showed that our Ge0.87Sn0.13 and Ge0.84Sn0.16 stacks have a direct band gap. Optically pumped laser emission at 2.6 µm (for 13% of Sn) and 3.1 µm (for 16% of Sn) was obtained in suspended GeSn micro-disks (after etching into pillars of the underlying Ge buffers). The lack of residual compressive strain at the free-standing edges of the micro-disks, which increases the directness of the bandgap (Whispering Gallery Mode propagation of the light), and the very high quality of the Ge0.84Sn0.16 cavities led to laser operation up to 180 K at an emission wavelength of 3.1 µm, with a lasing threshold of 377 kW/cm² at 25K.

Resume : Nanoscale structures introduce new ways for manipulating light coupling and trapping at the subwavelength scale. Light trapping structures that can effectively control and enhance light absorption such as nanowires[1], inverted nanopyramids[2], quasi-random patterns[3], nanospikes and nanocones[4] have all been reported, although mainly in the optical domain, with a few exceptions. In particular, structures are known as “black silicon” exhibit nearly zero reflection over a broad-spectrum range. The challenge is to incorporate such structures into real devices and not to compromise the optical enhancement by electrical losses such as surface recombination. Since black silicon devices exhibit large surface areas, minimising surface recombination is particularly difficult. For example, the black silicon solar cells reported thus far have yet not been able to compete with conventional silicon devices. Jihun Oh et al. have reported an 18.2% efficient interdigitated back contact (IBC) black silicon device[6]. They report that the doping profile is an important parameter for determining the dominant recombination process. They find that surface recombination only dominates for low doping density otherwise efficiency limitation is mainly due to Auger recombination. In contrast, Hele Sevin et al. report a 22.1% black silicon IBC device by overcoming surface recombination through a conformally deposited layer of alumina[7]. Here, we demonstrate the fabrication of quasi-random structures that have similar optical properties as black silicon and realise them by both wet and dry processing. We present a quantitative comparison of these structures both in the optical and electrical domain, assessing the impact of plasma etching by comparing the same nanostructures made by wet etching. Furthermore, it is interesting to understand whether the taper angle of the wet etched structure improves the antireflective property compared to the vertical walls achieved by dry etching. Ultimately, we hope to address the question whether we can use nanostructuring to improve the optical performance of solar cell devices without compromising their electrical efficiency. 1. Garnett, E. & Yang, P. Light trapping in silicon nanowire solar cells. Nano Lett. 10, 1082–7 (2010). 2. Zhou, S. et al. Wafer-Scale Integration of Inverted Nanopyramid Arrays for Advanced Light Trapping in Crystalline Silicon Thin Film Solar Cells. doi:10.1186/s11671-016-1397-6 3. Martins, E. R. et al. Deterministic quasi-random nanostructures for photon control. Nat. Commun. 4, 2665 (2013). 4. Wang, K. X., Yu, Z., Liu, V., Cui, Y. & Fan, S. Absorption enhancement in ultrathin crystalline silicon solar cells with antireflection and light-trapping nanocone gratings. Nano Lett. 12, 1616–1619 (2012). 6. Oh, J., Yuan, H.-C. & Branz, H. M. An 18.2%-efficient black silicon solar cell achieved through control of carrier recombination in nanostructures. Nat. Nanotechnol. 7, 743–748 (2012). 7. Savin, H. et al. Black silicon solar cells with interdigitated back contacts achieve 22.1% efficiency. Nat. Nanotechnol. 10, 1–6 (2015).

Resume : The extension of silicon photonics towards the mid infrared (mid-IR) spectral range has recently attracted a lot of attention. The development of photonic devices operating at these wavelengths is crucial for many applications including environmental and chemical sensing, astronomy and medicine. Recent works regarding the development of Ge-rich SiGe waveguides and interferometric devices on silicon will be presented. In particular, low-loss waveguides with good butt-coupling performance over a wide range of mid-IR wavelengths (from 5.5 µm up to 8.5 µm) will be shown, hence providing a key building block for further development of mid-infrared photonic integrated circuits. Specifically the design, fabrication and characterization of ultra-wideband couplers, resonators, and Mach Zehnder interferometers will be disclosed. These results provide a solid basis to develop a competitive mid-IR integrated platform which could potentially exploit the complete Ge transparency window, up to λ ≈ 15 µm.

Resume : New Si optical platforms harnessing many of the core capabilities of CMOS are rapidly changing the landscape of photonics. These platforms carry many basic components such as detectors, modulators and resonators, central for the development of optical data processing, linking and sensing applications. Seemingly, not easy to be realized in the indirect band gap group IV system is a laser light-source integrated with the well-established current Si based CMOS-electronics process technologies. Here, we will discuss forthcoming challenges on the way of a practical direct band gap Ge laser device1. Key issues involve the carrier inversion lifetime, parasitic absorption and the intravalley scattering to the L-levels, as revealed from recent synchrotron based pump und probe investigations. We present uniaxial tensile strained suspended GeOI micro-bridges2 combined with strain conserving cavities formed by parabolic mirrors in a corner cube configuration. We show the multimode cavity enhanced photo-luminescence (PL) up to 5 µm and a loss analysis of the mode spectrum. These results will be benchmarked by the lasing characteristics obtained at low temperature of optically pumped GeSn directly grown on Ge virtual substrate on silicon3. 1 R. Geiger et al. (2015). doi:10.3389/fmats.2015.00052. 2 M.J. Süess et al. (2013). NP. doi:10.1038/nphoton.2013.67. 3 S. Wirths et al. (2015). NP. doi:10.1038/nphoton.2014.321.

Resume : The ability to steer polarized optical fields is recognized as a central issue in photonics. Current approaches primarily rely on strong external magnetic fields or optical delay modulators, and do not allow the compact and monolithic design required for integrated architectures. Here we overcome such an obstacle by proposing a simple scheme based on engineered spin-dependent carrier dynamics. In particular, exploiting the multi-valley feature of the Germanium conduction band, we achieve all-optical control of chiral light emission, unveiling the key role of optical pumping. We investigate the state of the polarization of the direct-gap photoluminescence in bulk Ge and we provide an overview of the processes governing the recombination of carriers in the Γ valley. Our results anticipate spin-enhanced optoelectronic functionalities and provide a step forward towards the implementation of novel polarized light sources, such as Ge-based spin LEDs and spin lasers monolithically integrated on Si.

Resume : High n-type doping in germanium is essential for many electronic and optoelectronic applications especially for high performance Ohmic contacts, lasing and mid-infrared plasmonics. We report on the combination of in situ doping of Ge-on-Si epilayers and excimer laser annealing to improve the activation of phosphorous in germanium. An activated n-doping concentration of 8.8×10^(19) cm^(–3) has been achieved starting from an incorporated phosphorous concentration of 1.1×10^(20) cm^(–3). Secondary ion mass spectrometry measurements indicate that the box-like profile of as-deposited epilayers is preserved during the annealing treatment. Infrared reflectivity data fitted with a multi-layer Drude model indicate good uniformity in carrier concentration over a 350 nm thick layer. Photoluminescence demonstrates clear bandgap narrowing and an increased ratio of direct to indirect bandgap emission confirming the high doping densities achieved. The residual thermal in-plane strain of +3.7×10^(-3), as measured by Raman spectroscopy, exceeds the typical strain values of 2-2.5×10^(-3) achievable by conventional annealing methods, favoring the electron population of the Gamma-valley. Preliminary results achieved by optimizing both the growth procedure and the annealing treatment show that carrier concentration exceeding 1×10^(20) cm^(-3) can be obtained. [1] R. Pillarisetty, Nature 479, 324 (2011) [2] L. Baldassarre et al., Nano Lett. 15, 7225 (2015) [3] J. Frigerio et al., Phys. Rev. B 94, 085202 (2016)

Resume : Spintronics is an evolving concept for beyond CMOS-devices. In many of these concepts, spin polarized charge carriers get injected from a ferromagnetic contact into a semiconductor channel. Germanium is a good candidate for the semiconductor material due to the high electron and hole mobilities which lead to long spin lifetimes. Germanium itself can be easily integrated into the Si-platform. The ferromagnetic contact material should also be capable of being integrated into the Si-platform. In this work the formation of Mn5Ge3 on tensile strained Ge channels is investigated. The Ge channels are grown on Si (111) substrates by Molecular Beam Epitaxy (MBE). The fabrication of Mn5Ge3 can be carried out similarly to a silicidation process by evaporating Mn on Ge (111) and annealing to form the ferromagnetic Mn5Ge3 contact material. To investigate the formation of Mn5Ge3 we varied annealing parameters such as the ramp up time and the maximum temperature. Measurements of the magnetization using a superconducting quantum interference device show a ferromagnetic behavior for all samples, however, coercivity and remanescence vary. Using Mn5Ge3 as contact material, 3-terminal-devices using highly-doped Ge-channels are fabricated and Hanle-measurements are performed.

Resume : The growth of high-quality polycrystalline germanium on oxide is of interest to chip-level electronic-photonic integration on silicon wafer. High-quality polycrystalline germanium on silicon-oxide facilitates the fabrication of germanium devices in various applications including the back-end-of-line photonic device manufacturing. In this work, we present the large-grained polycrystalline germanium growth on oxide using reduced pressure chemical vapor deposition (RPCVD), which can have advantages in future device fabrications. In order to increase the polycrystalline germanium (poly-Ge) grain size for the reduction of the grain boundary density, we employed the selective growth technique and thin poly-silicon interlayer. Poly-Si interlayer and poly-Ge were sequentially grown in silicon-oxide trenches. The grain size of poly-Ge was investigated with the growth parameters, such as growth temperature, working pressure and growth rate. The crystal states of the grown germanium layers were characterized with high resolution X-ray diffraction (HRXRD) measurement, and the grain size was measured using electron backscattering diffraction (EBSD) and transmission electron microscopy (TEM). The measured grain size of the grown poly-Ge shows strong dependence on the crystalline quality of the poly-Si interlayer, indicating that much improvement on crystalline quality of poly-Ge can be achieved with proper optimization in our RPCVD selective growth technique.

Resume : Silicon Carbide (SiC) is a wide bandgap material with high breakdown fields, high thermal conductivity and high saturated drift velocities, with potential applications in high power devices and microelectromechanical systems (MEMS) in harsh environments. It has up to 200 different stable crystal structures (polytypes) all having different band gap and thus different electrical properties. Among the different polytypes, the cubic structure, referred as 3C-SiC, is the most thermodynamically stable at low growth temperatures (1100-1600 C), this allowing it to be hetero-epitaxially grown on Silicon substrates. The use of large-area substrates offers the possibility of economical and low-cost batch processing, which makes 3C-SiC more attractive for sensor and device applications and, given its small bandgap (when compared to the 4H-SiC polytype) of 2.36eV, for medium voltage applications (between 600 and 1600V). Though possible, the SiC/Si hetero-epitaxy suffers from the large lattice and thermal mismatch of the two semiconductors, 20% and 8% respectively, which give rise to both defects and stress. At the talk I will present the different defects, generated at the interface and into the film, and the associated stress as function of the crystal orientations and growth properties, and how they can be potentially reduced by the use of “compliance substrates”, with specific focus on growths on micrometric Silicon pillars.

Resume : The cubic polytype of silicon carbide (3C-SiC) is an interesting wide band gap material with outstanding properties, very promising for designing Micro-Electro-Mechanical Systems (MEMS) devices operating in harsh environment where Si-based devices reveal a shortage in their performance. The fabrication of suspended micromachined membranes triggers the interest for several applications such as pressure, tactile, flow, microfluid and acoustic sensors. In particular, 3C-SiC based membranes are advantageous for such devices operating in harsh and corrosive environments. In this contribution, we describe an approach that enables direct 3C-SiC membrane release, in real time, as the membrane grows. This new approach stems from controlling and exploiting the presence of voids in a Si epilayer, in stark contrast to the conventional view of voids as defects. This straightforward technique is expected to markedly simplify the fabrication process of membranes by reducing the fabrication duration and cost. In the presentation, we will first describe the growth of the complete 3C-SiC/Si/3C-SiC heterostructure on Si substrates, required for 3C-SiC membrane fabrication. The growth conditions and the defects in each layer will be commented based on TEM, XRD, SEM and AFM observations. Later on, the novel method for membrane fabrication will be presented. Finally, the advantages of this unprecedented technique compared to conventional techniques will be highlighted.

Resume : The growth of SiC on AlN thin films is challenging in many aspects. Indeed, the benefit of handling properly crystalline SiC/AlN heterostructures could open the way toward the design of innovative heterostructures, taking advantages both of the electrical and mechanical properties of SiC and AlN. Our group has recently communicated on the potential advantages of fully crystalline SiC membranes on Si substrates (R. Khazaka et al. APL 110, 081602 (2017)), but some applications require to electrically isolate the upper and lower SiC membranes. In this perspective, AlN is very promising regarding its high bandgap and its ability to be grown on SiC/Si templates. Nevertheless, we have to face different major concerns as SiC growth requires high temperatures and gas environment which could severely damage the AlN. In this presentation, we show the routes we adopt to grow, by CVD, cubic SiC on AlN(0001) thin films. We use either AlN thin films grown by MBE on Si(111) substrates or 3C-SiC/Si(111) CVD templates. We investigate the influence of the initial thermal ramp up, preceding the SiC growth. It is shown that the preservation of a surface suitable for SiC growth requires the use of carbon- or silicon- rich precursor gases diluted in nitrogen. We present also the characteristics of the SiC films grown on the AlN films according to the growth conditions. It is shown that, due to the site competition effect between C and N, a strong self-doping can occur during the growth.

Resume : Silicon carbide is very attractive material for microelectronic integrated circuits production due to chemical, electrical properties and also huge radiation and thermal durability. Silicon carbide substrates are expensive for serial production and it schould be found a method to grown defects free epitaxial silicon carbide layers on top of cheep silicon substrates. Silicon carbide layers grown directly on silicon are defect-riched due to significant lattice misfit and difference of thermal expansion coefficient. Additionally, formation of porous layer under the silicon carbide results in decrease of elastic strain and consequently improves the structural quality of silicon carbide. One can suggest that additional growth of silicon or silicon-germanium patterned layers during SiC growth will leads to noticeable decrease of growth temperature as well as improvement of the quality of silicon carbide. The main goal of the present work is investigation of high temperature carbidization process of silicon wafers with epitaxial patterned buffer layers.

Resume : Developing silicon based thermoelectric generators is subject to high interest in the thermoelectric energy harvesting community. Compared to conventional materials used for commercial thermoelectric generators, silicon has the advantages to be the most wide spread semi-conductor material, environmentally less harmful and benefits from existing facilities and processing technologies developed for low cost mass production. However, the high thermal conductivity of bulk silicon makes it a very poor thermoelectric material especially for near room temperature applications. Hence, thermal conductivity reduction is the key to upgrade silicon as an efficient thermoelectric material. Efforts toward thermal conductivity reduction are oriented toward reducing the phononic heat transport, which is the dominant contribution. This reduction can be achieved by reducing the phonon mean free path and/or the phonon group velocity e.g. by use of thin films [1], nanowires [2], addition of impurities [3], silicon nano-patterning [4]… . Previous works have shown that periodical holes structures called phononic crystals are able to downscale further the thermal conductivity with minor impact on the electrical conductivity [5]. The combination of the thin film and the phononic crystal enables reaching a thermal conductivity from 34 W∙m^(-1)∙K^(-1) [6] to even as low as 2 W∙m^(-1)∙K^(-1) [4]. In this paper we focus on the potential thermoelectric properties improvement of silicon by means of a planar phononic thin silicon film based thermoelectric generator. The expected performance is benchmarked with respect to existing commercial thermoelectric generator. We performed a FEM benchmarking of our optimized thin silicon based TEG with the commercial Micropelt’s TEG [7], [8] for 20 W∙m^(-1)∙K^(-1) and 4 W∙m^(-1)∙K^(-1) hypotheses as silicon’s thermal conductivity, near room temperature range and for two cooling conditions : natural convection without heat sink and natural convection with a small-capacity heat sink. Results show an improved exploitation of the thermal gradient into the thermoelectric material due the planar architecture thus leading to a maximized harvested energy even without need for massive heat sink. Those results open perspectives in the field of autonomous sensor nodes based on low cost and scaled silicon material production. Bibliography: [1] M. Haras et al., « Fabrication of integrated micrometer platform for thermoelectric measurements », in 2014 IEEE International Electron Devices Meeting, 2014, p. 8.5.1-8.5.4. [2] A. I. Hochbaum et al., « Enhanced thermoelectric performance of rough silicon nanowires », Nature, vol. 451, no 7175, p. 163‑167, janv. 2008. [3] J.-H. Lee, G. A. Galli, et J. C. Grossman, « Nanoporous Si as an Efficient Thermoelectric Material », Nano Lett., vol. 8, no 11, p. 3750‑3754, nov. 2008. [4] J. Tang et al., « Holey Silicon as an Efficient Thermoelectric Material », Nano Lett., vol. 10, no 10, p. 4279‑4283, oct. 2010. [5] J.-K. Yu, S. Mitrovic, D. Tham, J. Varghese, et J. R. Heath, « Reduction of thermal conductivity in phononic nanomesh structures », Nat Nano, vol. 5, no 10, p. 718‑721, oct. 2010. [6] M. Haras et al., « Fabrication of Thin-Film Silicon Membranes With Phononic Crystals for Thermal Conductivity Measurements », IEEE Electron Device Letters, vol. 37, no 10, p. 1358‑1361, oct. 2016. [7] H. Bottner, « Thermoelectric micro devices: current state, recent developments and future aspects for technological progress and applications », in Twenty-First International Conference on Thermoelectrics, 2002. Proceedings ICT ’02, 2002, p. 511‑518. [8] H. Bottner, « Micropelt miniaturized thermoelectric devices: small size, high cooling power densities, short response time », in ICT 2005. 24th International Conference on Thermoelectrics, 2005., 2005, p. 1‑8.

Resume : Self-assembled diphenylalanine (FF) peptide nanotubes (PNTs) have attracted significant attention due to their well-ordered supramolecular structure and wide range of functional capabilities that may enable potential nanobiotechnology applications. However, self-assembled PNTs are generally inhomogenous at the macroscale, which has limited their potential use. Reproducibly controlling the assembly and alignment of PNTs is therefore critical to enable the widespread use of PNTs, e.g., in sensing applications. In this study, a surface patterning technique based on UV/ozone exposure through a shadow mask is used to align PNTs. Exposed regions become hydrophilic, leading to directed spreading of the FF solution and alignment of the PNTs that improves as the difference in wettability between adjacent regions increases, suggestion that the difference in wettability between region leads to a chemical force, which drives the alignment process. Alignment is further found to depend on the concentration and temperature-dependent diameter of the PNTs formed and the size of the hydroplic area. Finally, aligned PNT decorated with silver nanoparticles are used as templates to sense an analyte molecule (TMPyP), at different concentrations using surface enhanced Raman spectroscopy. Using aligned PNTs as template for SERS-active materials may provide route to improving the reproducibility of the SERS signal by tailoring the density and location of the materials, and may enable single molecule detections.

Resume : SiO2/ZrO2 asymmetric dual layered tunnel oxide was fabricated, and examined in terms of its program/erase characteristics. A lower program voltage for the target Vth indicates a faster programming benefit, which was attributed to the reduced F-N tunneling barrier due to the insertion of ZrO2. The retention behaviors of the hybrid tunnel oxides were also investigated by comparing the Vth obtained before baking with that obtained after baking at 125C. Among the combinations in thickness between SiO2 and ZrO2, the hybrid oxide having thin SiO2 combination (3 nm) yields poor retention property compared with that having thick SiO2 combination (4 nm). Such degradation in retention property was understood in terms of diffusion of Zr into SiO2 during the subsequent heat budget. The diffusion of Zr in SiO2 brings up a trade-off between the benefits of the program and erase speed and the disbenefit of the degradation in retention characteristics. That is, it increases the program and erase speed, while it deteriorates the retention characteristic. Thus, a hybrid tunnel oxide combination with relatively thick SiO2 reveals better retention behavior compared to those of reference samples. In addition, the trap density of ZrO2 was obtained by ISPP test. The result obtained from ISPP test indicates that ZrO2 in the hybrid tunnel oxide serves as a tunneling dielectric without effect on the charge storage.

Resume : Observation of liquid-containing materials in transmission electron microscope is now very common analytic methodology for material scientists. Among the methods, trapping liquid between micro-fabricated silicon nitride windows, is more preferred method since it is consistent, versatile, and easy to prepare, compared to graphene liquid cells. Many vendors and research groups has developed and commercialized their liquid chip with noble structure, optimized to their research targets. Silicon nitride window liquid cell technique has many advantages, but there are also many restrictions, such as resolution degradation from liquid thickening and limitation in selection of solution due to the wettability to membrane. Introducing various metal mesh or grating pattern to nitride membrane, is shown to affect bulging effect in vacuum and wettability of membrane. Also, isolating each cell with patterned metal grating prevents solution vaporization from electron beam induced radiolysis effect.

Resume : Copper (Cu) has been considered as an alternative material of Al for an interconnect metallization in modern ULSI devices due to its low resistivity and good electro-migration resistance. In our current devices such as dynamic random access memory and flash memory, Cu also has been widely used as a metal line at the back end of line process. Cu film was deposited on the damascene pattern by well-known electro-plating method. It was filled conformally in the trench pattern and shows favorable resistivity for the device performance. However, Cu hillocks were observed at the wafer edge area which is the range from 140mm to 150mm, and it showed slightly lower device yield in the same area. Because the generation of metal hillocks usually occurred by the compressive stress induced by the thermal budget which applied to the wafers, and we observed that the Cu hillocks were significantly decreased by the treatments to evacuate the residual Fluorine (F) from the chamber using the F reducing gases such as SiH4 and NH3, we modified the in-situ cleaning process to minimized the contact of the wafers to the heater and the residual F to suppress the Cu hillocks. In this paper, we focused the thermal budget and the F which can affect to the wafers during the in-situ cleaning process as main causes of the Cu hillocks. Thus, the modifications of the purge steps and the addition of the F removal steps using SiH4 and NH3 gases in the in-situ cleaning process were conducted to minimize the thermal budget and to remove the effect of F on the formation of Cu hillocks. Using the above methods, the formation of Cu hillocks significantly reduced from around 3600ea to 230ea (93.4% decrease). To date, because the F effect on the Cu hillock formation has rarely been studied, the mechanism for proving the F effect is proposed and discussed.

Resume : A vertically multiple stacked nanowire FET (VMS-NWFET) has been considered as a promising candidate for the suppression of short-channel effects, high performance, and ultimate scalability [1]. A junctionless-mode (JM) VMS-NWFET has also been presented due to its reduced variability and simple fabrication process [2]. In addition, the JM VMS-NWFET showed a more suppressed low-frequency noise level than an inversion-mode (IM) VMS-NWFET due to its inherent bulk conduction [3]. As pixel sizes are scaled down, CMOS image sensor (CIS) demands improved robustness against temporal noise such as flicker noise and random telegraph signals. Accordingly, the JM VMS-NWFET is expected to be used as a source follower (SF) for CIS. In this work, the linearity of the SF gain, an important characteristic to avoid distortion of a color image, was measured and compared in the JM VMS-NWFET and the IM VMS-NWFET. It was found that the linearity of the SF gain in the JM VMS-NWFET is superior to that in the IM VMS-NWFET according to the applied gate voltage (VG) as the trap-related noise is lowered by bulk conduction in the JM. Furthermore, the improvement in the linearity of the SF gain is greater with high channel doping in the JM VMS-NWFET. However, optimization of the doping concentration is necessary because an adverse drop in the threshold voltage can occur when the doping concentration is too high. [1] B.-H. Lee et al., Nano Lett., vol. 15, no. 12, pp. 8056–8061, 2015. [2] B.-H. Lee et al., Nano Lett., vol. 16, no. 3, pp. 1840–1847, 2016. [3] T. Bang et al., IEEE EDL, vol. 38, no. 1, pp. 40–43, 2017.

Resume : GeSn with quasi-direct band gap is one of the most promising semiconductor materials for light emitters integrated with CMOS technology. The equilibrium solid solubility limit (SSL) of Sn in Ge is in the range of 0.5 % and the predicted theoretical Sn concentration needed for the direct band gap formation is above 5 %. This means that GeSn with direct band gap is metastable and any related material process cannot be thermal equilibrium. Here we propose to utilize strongly non-equilibrium processing i.e. ion implantation followed by millisecond range flash lamp annealing (FLA), for doping and the formation of Ohmic contacts with low contact resistance on Ge0.95Sn0.05. The effective carrier concentration in P+ implanted Ge0.95Sn0.05 layer followed by FLA for 3 ms is above 5×10^19cm-3 with a specific contact resistance rc=4×10^-6Ωcm2. NiGe for Ohmic contact is made by Ni diffusion into GeSn during a single 3 ms long flash pulse. TEM images reveal that NiGe is polycrystalline but with an atomically sharp interface between the metal contact and GeSn. The influence of non-equilibrium processing (ion implantation and FLA) on the optical, electrical and microstructural properties of the GeSn layer grown by MBE on Si will be discussed in details.

Resume : An approach to form polycrystalline GeSn thin films with high Sn composition and large size grains by depositing Sn/Ge in cycles at low temperature was proposed. Initially, Sn self-assembled islands was grown on insulating substrate, which induces in-situ sputtered Ge to crystallization to form GeSn nanocrystalline thin films with high Sn composition. Thick GeSn crystalline films were then achieved by circularly deposition of Sn/Ge layers at low temperature. The grain size of GeSn with Sn content of 15% formed after stacking 20 periods of Sn(5nm)/Ge(10nm) layers reaches about 1μm. The hole mobility of polycrystalline GeSn thin films up to 24.9cm2•V-1•s-1 is achieved with process temperature of less than 450oC. The cutoff wavelength in the response spectrum extends to 2000nm for the polycrystalline GeSn photoconductors. Those results suggest that polycrystalline GeSn films are promising for high performance thin film transistors and short wave infrared photodetector arrays on insulating substrate.

Resume : Recently, chalcogenide materials is expected to use for neuromorphic devices due to possibilities of multi resistance levels, high speed, long retention, and low power consumption. However, it is still not reported how to improve its benefits of high speed and low power consumption since the conventional Te-based chalcogenide has serious limitation in the multi-level, high speed switching and low power consumption performances for the synaptic neural network. In this work, we have found that doped chalcogenide materials, for example, Bi doped In3SbTe2 (Bi-IST) has multi-level transition at relatively lower temperatures, the lower activation energy, the fast switching performance. Fabricating neuromorphic devices with doped chalcogenide, we have investigated that the depression and potentiation process are connected to the set operation and reset operation, respectively, and discussed the relationship among the fast phase transition, multi-synaptic signals for neuromorphic system and multi-bit memory as well as the low power operations of long-term potentiation (LTP) and long-term depression (LTD) with STDP rule.

Resume : Cu through silicon vias (TSVs) still requires some challenging issues related with smooth Cu seed layer and strong adhesive diffusion barrier to preventing defects due to Cu diffusion and chemo-mechanical polishing. In this work, we have suggested atomic layer deposited (ALD) WCN thin films as a promising diffusion barrier for Cu TSVs. For the deep TSV with high aspect ratio of 30:1 and 20nm diameter, step coverage of ALD-WCN is comparable with carbon nanotube (CNT) and Contact resistance of Cu/WCN/Si TSVs has as low as 9-10 Ω/contact. It’s thermal stability was measured after 700˚C for 30 min. 90% of Cu/WCN/Si TSVs are maintained within the 10% deviation from the initial value. In contrast, Cu/TiN/Si, Cu/TaN/Si, and Cu/WN/Si TSVs shows severe deviation after the same annealing conditions. Mean time to failure was also investigated with 4 different TSVs. As a result, 85 % of the Cu/WCN/Si interconnect lines are not failed till over 106 s, which means that the life time of the Cu/WCN/Si is longer than those of other interconnect lines by one order of magnitude. Furthermore, after CMP process, the defect density is almost zero in the case of WCN diffusion barrier. The excellent performance of the WCN diffusion barrier seems to be originated by the compressive film stress and strong adhesion with silicon side wall.

Resume : In CMOS devices of sub-0.1 um regime, the thickness of SiO2 gate oxide is less than 1.5 nm, where the leakage current rises to an unacceptable limit. One of the alternative is to replace SiO2 with a material with higher dielectric constant, and HfO2 is one of the most promising high-k materials. Ultra-thin HfO2 films of 3.5, 5.0, and 8.0 nm were prepared, respectively, on silicon substrates by using ALD method. Through the analyses of XRR, XPS and TEM for HfO2 films with or without surface cleaning, surface contamination layer was identified and the thickness of surface contamination layer were measured. X-Ray specular reflectivity at a particular incidence angle increased after the cleaning of the sample, and decreased again to a similar value to the reflectivity of as-received sample after being exposed to atmosphere for two weeks. XPS results showed that the changes in reflectivity due to the cleaning were caused by varying amount of surface contamination of the sample. XRR curves changed and the positions of thickness fringes were different for the identical sample with or without the surface cleaning, and the thicknesses determined from Fourier analyses of the XRR curves were different due to different surface contamination. Fourier analysis of the XRR curve measured by synchrotron source revealed the existence of a surface contamination layer of about 1 nm thickness. Simulation for XRR curve showed the best fit to data when contamination layer of about 1 nm thickness was considered, and the result was consistent with that of the Fourier analysis. Finally, a surface contamination layer was identified, and the thickness of the contamination layer as well as the thicknesses of HfO2 films were determined precisely.

Resume : Our development focused on metal oxide chemiresistive gas sensor using TiO2, and we have fabricated platform including Pt microheater heater and interdigitated electrode (IDE) by micro-electro-mechanical system (MEMS) processes. Specified Pd decorated TiO2 thin film have been mounted on the top of the IDE by radio-frequency (RF) sputtering with 300 W of RF power and gas sensing performances have been investigated for hydrogen gas detection. The gas sensor with 200 nm TiO2 thin film under 200 °C of operating temperature showed higher sensitivity with less than 50 mW power consumption. The microstructures of material were systemically characterized by FESEM, AFM and X-ray diffraction patterns and we also discussed the effect of microstructure to gas sensing properties.

Resume : Rapidly expanding interests in the technology of the two-dimensional (2D) materials are stimulated by highly promising advantages demonstrated for development of electronic devices based a monolayer of a 2D-material. Low power consumption, unique characteristics and nanoscaling of the devices are the most attractive features for practical applications. It is already known that depending on the number of monolayers, the band gap of the MoS2 can be modified and a variation of parameters with spectrum can be intentionally modified by the number of MoS2 monolayers in the photonic devices. In this work we developed an original technological method to synthesize a predictable number of the MoS2 monolayers by intentional control of the metallic Mo precursor. MoS2 films were prepared by sulfurization of Mo layers deposited on the substrate. As synthesized structures were characterized by AFM and Raman scattering measurements. Technological deposition and sulfurization parameter influence on the properties of the MoS2 films were investigated. We demonstrate that intentionally changing deposited Mo film thickness from < 1 nm to 4 nm we can change the number of monolayers, after sulfurization, in the resulting MoS2 films from 1 to ?4.

Resume : Chemical Bath Deposition (CBD) is a simple and inexpensive technique for thin film deposition of a variety of semiconductors upon substrates such as silicon and gallium arsenide. Nevertheless, this technique experiences some drawbacks such as change of reactant concentrations and spatial non-uniformity. Liquid flow deposition (LFD) is a variation of CBD with potentially improved performance. In the current research LFD was studied using a custom made reactor. The deposition of lead sulfide (PbS) on gallium arsenide (GaAs) substrate was explored as a test case. PbS is widely studied for different applications such as photovoltaic cells, IR detectors and thermoelectric devices. The main objectives of the current research were to enhance understanding of thin film deposition by comparing the LFD and CBD methods, and optimization of PbS thin film deposition using LFD. High Resolution Scanning Electron Microscopy (HR-SEM) and X-ray Diffraction (XRD) revealed films with <110> oriented crystals with ~800 nm grain size for both methods. There were much less particles precipitating on the film surface in the case of LFD compared to CBD. The initial growth rate of PbS films via LFD was found to be lower than in CBD, resulting in thinner film thickness and suggesting that LFD is more suitable for growing films via the ion-by-ion mechanism. Kinetic studies show that the maximal growth rate in the reactor was achieved when residence time corresponded to half of the induction time. Moreover, as expected, the growth rate in LFD reactor increases with time up to 60 nm/min after 2 hours of deposition, while in CBD the growth rate drops after half an hour of deposition.

Resume : Wafer to wafer bonding was studied for wafer level packaging of various high integrated and multi-dimensional sensors. These wafer to wafer bonds were performed at low temperatures under 450 °C and involved either field-assisted silicon to glass anodic bonding or a eutectic bond between wafers using a gold (Au) and other metals. And, it is essential to study that low temperature bonding for heterogeneous wafers, because the higher temperature bonding may induce cracks, defects, bowing, and destruction by different thermal expansion coefficients of the heterogeneous wafers. We investigate low process temperature eutectic bonding with Au-indium (In) metal alloy for the application of III-V compound semiconductor based magnet sensor devices on silicon wafer. The bonding temperatures of Au-In is 210 °C, respectively. The indium layer melts and dissolves the Au layer to form a mixture of liquid and solid. A field emission scanning electron microscopy (FE-SEM) was used to determine the excellent bonding quality of the interface of wafer to wafer bonding. An energy-dispersive X-ray spectroscopy (EDS) was employed to determine the composition of the resulting Au-In wafer to wafer bonds. The resulting bonds have de-bonding temperature of Au-In greater than 450 °C, respectively. The bonding strength of Au-In wafer to wafer bonding is 13.4 MPa. Due to the low process temperature, the stress on the bonded structure caused by thermal expansion mismatch is reduced.

Resume : Various fabrication technologies for atomic force microscopy (AFM) probes have been investigated, emphasizing the fabrication of high-aspect-ratio silicon tip, which can be integrated with micromachining techniques. Currently, most AFM probes are formed directly by anisotropically wet etching. In this work, proposed processes for making sharp silicon tip are classified into three categories; (1) anisotropic etching of silicon using various concentrations of KOH solution; (2) self-sharpening technique for anisotropically wet etching, which is used etch mask aligned to <310> directions; and (3) combined anisotropic etching with isotropic etching of silicon using various compositions of nitric acid, water, and hydrofluoric acid. Sharp silicon tips were achieved using a matrix of etching conditions, and results were analyzed using a scanning electron microscope(SEM). Both the tips and cantilevers are simultaneously formed by a masked-maskless combined anisotropic etching process. As a result, novel high-aspect-ratio silicon tip shapes have been achieved and integrated with AFM cantilevers. A simple and high yield method for the fabrication of cantilever with a high-aspect-ratio silicon tip will be presented in the conference.

Resume : The growth of a high quality epitaxial layer requires a clean initial substrate surface. In the difficult case of hetero-epitaxy on Si, optimization of the pre-epi clean sequence focuses on surface preparation and efficient Si de-oxidation. The classical combination of a HF wet etching followed by high temperature H2 bake (> 950C) sequence will efficiently de-oxidized the Si surface with perfect step and terraces surface morphology. However the implementation of this pre-epi clean sequence in a CMOS integration scheme is limited due to integration driven thermal budget constraints leading to reflow and/or relaxation of effects. In that context, we are studying the use of an in-situ pre-epitaxy clean in combination with a low thermal H2 bake budget (< 650C) for III-V hetero-epitaxy on Si as an alternative to the standard procedure for Si surface preparation. We developed an in-situ dry etch approach consisting of fluorine based chemistry as an alternative option. We will benchmark the different options (wet-etch versus dry etch, with and without high temperature H2 bake) and characterize them on blanket Si substrates in terms of Si selectivity, Si surface roughness and residual contaminations (O, F, C, ...) after in-situ dry etch process. In a final part, we will study the impact of the fluorine based in-situ dry etch process on Si/SiO2 patterned substrate prior to III-V selective area epitaxy.

Resume : Tunneling field-effect-transistor (TFET) has been strongly investigated as a promising candidate device for the low power application due to steeper subthreshold swing, low off current and its scalability. However, it has still several challenges since TFET needs abrupt junction between source and channel as well as requires low-doped substrate in the form of p-i-n structure. Particularly, modulating symmetric threshold voltage (Vth) for the realization of CMOS inverters is of great interest. Controlling gate electrode’s work-function is the way to tune Vth of SOI-like TFETs. In this study, all ALD gate stack (HfAlOx/TiN) was used, where ALD TiN thickness was varied to modulate Vth in n- and p-MOS TFETs, and bias temperature instability against the electrical stress was compared. We fabricated the gate-last like TFET on the 6-inch p-type SOI substrate. After thinning SOI to 50 nm by oxidation, wet etching and active formation steps were followed. To mimic gate last process, BF2 and As were implanted (10 keV, 3.0×1014 cm-2) into the source and drain region, respectively, followed by dopant activation annealing at 950 ˚C for 5 seconds. Gate stack with ALD HfAlOx (Al 25%, HAO) using TEMA-Hf and H2O as well as ALD TiN using TiCl4 and NH3 was employed, where ALD TiN was with thickness of 5 nm and 10 nm. To reduce the contact resistance, we added PVD TiN as a capping metal. Total thickness was kept to 150 nm. The subsequent processes followed the conventional transistor processes. As a reference, both MOSFET and TFET with PVD TiN of 150 nm thickness were fabricated as well.Compared to PVD TiN, ALD TiN enhances Vth and its impact is increased further with thicker TiN for both MOSFET and TFETs. In TFETs ALD TiN of thickness of 5 nm and 10 nm induces 60 mV and 120 mV shift of Vth, respectively, in n-TFET while 5 nm-thick ALD TiN and 10 nm-thick ALD TiN of p-TFET leads to 90 mV and 170 mV shift, respectively, compared to PVD TiN-based n-TFET and p-TFET. The extracted interface traps state (Nit) values from Icp measurement are ~7.2x1011 cm-2, ~6.0x1011 cm-2, and ~8.5x1011cm-2 for ALD 5nm-thick TFET, ALD 10 nm-thick TFET, and reference PVD TiN TFET, respectively, proving that ALD TiN is superior to PVD TiN in terms of the electrical Vth stability due to the absence of plasm-induced damage. To obtain the Vth modulation knob for the realization of CMOS TFETs, we demonstrated low temperature ALD TiN gated TFETs with Vth tunability by varying TiN thickness. Compared with PVD TiN, adding ALD TiN into gate electrode leads to Vth shift up to 170 mV as well as lower Nit generation against the electrical stress. Our results provide the feasibility of Vth modulation of TFET with ALD TiN thickness variation. [Acknowledgement]: This work was supported by the Future Semiconductor Device Technology Development Program (10044842) funded By MOTIE (Ministry of Trade, Industry & Energy) and KSRC (Korea Semiconductor Research Consortium).

Resume : GeSn group-IV material is experiencing a renewed interest partly due to the recent demonstration of laser emission from GeSn layers grown on Ge/Si(001)-virtual substrates. It has been predicted an indirect-to-direct transition for unstrained GeSn alloys with Sn concentrations in the range from 6 to 12%. However, two major issues have to be overcome to obtain high cristalline quality GeSn layers which are mainly the low equilibrium solubilty (<1%) of Sn in Ge and the large lattice mismatch (~15%) between Ge and -Sn. NWs could offer the possibility to grow high cristalline quality GeSn material thanks to the strain relaxation on the large specific surface developed. In this work, we have investigated Sn incorporation in Ge NWs grown by chemical vapor deposition (CVD) via the vapor-liquid-solid mechanism (VLS). This growth process is a non-equilibrium one which should facilitate the incorporation of Sn into the Ge NWs. In our experiments, GeH4 and SnCl4 were used as gas precursors. Several growth conditions such as the growth temperature, the SnCl4/GeH4 ratio, and the total pressure in the reactor were varied in order to determine the best growth conditions for incorporating a maximum of Sn in the Ge NWs. Sn concentrations in the Au catalysts were measured using EDX and radial Sn distribution in Ge NWs was obtained by Auger profiling and/or STEM-EDX measurements. The obtained results will be presented.

Resume : A theoretical approach to predict temperature gradients during Pulsed Laser Induced Epitaxy (PLIE) of SiGe alloys with SiO2 hard masks is proposed and obtained results are compared with experimental ones. PLIE is based on laser induced fast melting/solidification processes that allows fast processing and in-situ monitoring of growing SiGe based alloys. Predicting the layer structure and the energy densities as well as number of laser pulses, needed for the successful growth of high quality SiGe based alloys is essential for its use in the fabrication of future integrated laser devices. A deeper understanding of the growth process is required and a theoretical approach has therefore been followed, using Finite Element Methods (FEM). Simulations were carried out with Software Comsol, by evaluating a one dimensional unsteady melting-solidification thermal problem, using the effective specific heat technique, coupled to a set of unsteady convection diffusion equations (activated during the melting process) of the different involved layers. Different scenarios were considered: firstly, the analysis of a 200nm Ge layer over the Si(100) wafer for two values of applied laser fluences (0.3 and 0.7 J/cm^2) up to 50 laser pulses. Comparison of melting times and concentrations distributions between the numerical results and the experimental ones served to validate the mathematical model and the used parameters. Secondly, 1D numerical simulations of SiO2 hardmask with different thicknesses over the previous layout were considered in order to quantify the optimal thickness to prevent melting of the hard mask. The model developed in this work will be applied in future over 3D problems making the design and selection of suitable masks easier.

Resume : Nanowires (NWs) are emerging building blocks for the bottom–up assembly of nanodevices and functional systems, holding promise for a variety of field applications including chemical and biological sensors, field effect transistors, light-emitting diodes, optoelectronics, and photodetectors. There have been extensive studies on their synthesis, with considerable advances made in the control of the structure, electrical, and thermal properties. Silicon and silicon-germanium nanowires (SiNWs/SiGeNWs) appear particularly important because of their potential applications in microelectronics areas and their ability to perform band-engineering in order to improve carrier’s mobility nanowires. However, placement of nanowires and post growth manipulation in a coherent and useful way continues to be a considerable challenge. In this context we will present two complementary strategies to localize precisely the Si and SiGe nanowires on CMOS chip. (i) First, using dielectrophoresis technique and second, (ii) direct growth of NW assembly on pre-patterned electrodes using Vapor-liquid-solid (VLS) mechanism.

Resume : The need for high-bandwidth interconnects with reduced power consumption is becoming critical with the advent of cloud computing. The integration of Si photonics on CMOS platforms is the subject of intensive developments. Ge-based electro-optical modules, such as integrated light sources, variable optical attenuators, photodetectors and modulators, receive a lot of attention owing to their compatibility with Si and promising performance. Epitaxial Ge, grown on Si, plays a key role in the fabrication of these devices. However, Ge/Si heterostructures typically suffer from high threading dislocation and interface trap densities, which degrade the final performance (Chen et al., JAP, 119, 213105 (2016)). Here, the post Ge epitaxy thermal treatment is adjusted to demonstrate free-carrier lifetimes as high as 7ns in 1µm-thick Ge virtual substrates. In addition, we compare different schemes for the passivation of polished, 600nm-thick, Ge layers having a controlled threading dislocation density of 6E7cm-3. Time-resolved photoluminescence measurements allow for the extraction of surface recombination velocities, taking into account the Ge/Si interface recombination velocity as determined by Srinivasan et al. (APL, 108, 211101 (2016)). The use of either an epitaxially grown Si cap or GeO2 based passivation approach allows a significant increase in carrier lifetime in Ge, with respect to unpassivated Ge and to Ge capped with SiO2 as standardly used for device isolation.

Resume : Gallium phosphide with a small amount of nitrogen and arsenic is a promising material for silicon based integration due to its lattice parameters and a wide range of band gaps (1.5 - 2.0 eV) [1]. It is still a serious challenge to grow a high quality GaP(NAs) layers on silicon but multijunction solar cells [2] and light emitting diodes [3] were already fabricated. Parameters of semiconductor devices are also depend on post-growth processing steps such lithography and etching. Precise etch depth control is needed for example to separate study of layers properties in device structure and also for a contacts fabrication. Dry etching is the most widely used processes in industry and research but a probability of active layer degradation due to high energy particles exists. This paper presents some results concerning wet etching of GaP(NAs) layers grown by MBE on silicon wafer. As a result, structures for direct measuring of sub-cells characteristics in GaP(NAs)-based dual-junction solar cell were made. The I-V and CV-curves for top and bottom sub-cells were successfully measured. This work is supported by the Russian science foundation, grant RSCF, project No 17-19-01482 [1] J. F. Geisz, D. J. Friedman, and S. R. Kurtz, in Proceedings of the 29th IEEE PVSC (New Orleans, LA,2002), p. 864. [2] A.S. Gudovskikh et al. Proc. 29th EU PVSEC 2014 Amsterdam Netherlands 2014 4CV.3.3 [3] A. V. Babichev et al. Semiconductors (2014) V. 48. pp 501–504

Resume : In recent years, the investigation of Multi-gate Metal Oxide Semiconductor Field Effect Transistors (MG MOSFET) has attracted more attention due to their high electrical performance and scalability provided for nanoelectronic applications. In this context, to analyze the Junctionless Gate All Around (JL GAA) MOSFETs is a challenge because the parasitic phenomena appearing at deep submicron level, where the short channel and ageing effects are considered the critical negative aspects that need to be investigated carefully. Up to our knowledge, no investigations have been carried out considering both electrical performance and device degradation-related ageing effects. In this context, in this work we present a numerical investigation of junctionless GAA MOSFET including degradation-related ageing effects to study the nanoscale JLGAA MOSFET Reliability against the ageing phenomenon. Moreover, the effect of the stress time and channel length on the device performance is presented. In order to show the impact of the proposed approach on the electronics circuits designing, the developed model has been implemented to study the performance behavior of voltage amplifier circuit including degradation-related ageing effects. Therefore, the proposed approach can offer new insights regarding the investigation and simulation of the nanoelectronic circuits including the degradation-related ageing effects.

Resume : Lattice-matched systems of III-V compounds grown on Si substrates are very promising for optoelectronic and photovoltaic application. The efficiency of III-V/Si multijunction solar cells could exceed 50%. GaP provides better charge carrier mobilities and higher bandgap value (2.26 eV) compared to that of a-Si:H. This results in GaP/Si heterojunction being advantageous for high-efficient solar cells. According to numeric simulation, electrical properties of GaP/Si heterostructures depend on whether Ga-Si or P-Si bonds are formed. However, epitaxial growth of GaP requires high temperatures (> 600°C) which lead to interface blurring and the formation of both types of bonds at the same time. In this work, we present our results in growing GaP/Si structures on (100) Si substrates by low-temperature PE-ALD method. The growing process is tuned to start with Ga or P atoms. The influence of abrupt Ga-Si and P-Si interface on band bending and band offset will be studied by capacitance measurement techniques.

Resume : In recent years, Vertical 4H-SiC Power MOSFETs exhibit superior performance relative to lateral MOSFETs due to the higher carrier mobility in the c-plane 4H–SiC, high break-down electric field and high thermal conductivity. However, these devices suffer from low values of the channel mobility in the inversion layer due to the high interface state density (DIT) near the SiC/SiO2 interface, which leads to the degradation of the device Figures of Merit such as: on-resistance, break-down voltage and the derived current. The main objective of this work is to investigate the reliability performance of Vertical 4H-SiC Power MOSFET device including interface state density effects. Up to our knowledge, few investigations have been carried out considering both electrical performance and device degradation-related interface traps effects. In this context, in this work we present a numerical investigation of Vertical 4H-SiC Power MOSFET including degradation-related interfacial defects to study the device reliability. Moreover, the effect of the channel length, oxide permittivity and cannel doping effects on the device performance is presented. The proposed approach can offer new insights regarding the investigation of the power electronic devices including the degradation-related interfacial defects.

Resume : As fundamental physical limits of Silicon-based integrated circuits are arising, novel materials such as 2D Transition Metal Dichalcogenides (TMDs) are gaining significant scientific importance. Within this perspective, 2D WSe2 monolayers are of great interest due to the unique ambipolar behavior of the semiconductor enabling both p- and n-type devices. Also, combined with other 2D materials, WSe2 shows to be the material of interest for a next generation of tunneling or low power transistors. Nonetheless, as Raman spectroscopy is considered to be a main technique for TMD characterization, careful interpretation of the Raman spectra of WSe2 monolayers is made difficult by the overlap of the main two first-order Raman active vibrational modes at ~250 cm-1. Therefore in a first stage of this work, we perform an in-depth Raman spectroscopy study on high crystalline quality WSe2 exfoliated flakes for an improved interpretation of the Raman spectra of the WSe2 monolayers grown by Gas Source Molecular Beam Epitaxy (GSMBE). In a second stage, we present that the combination of Raman spectroscopy with other physical characterization techniques (e.g. RHEED, RBS, XPS, AFM and TEM) allows a better understanding on the structural and chemical properties of the WSe2 monolayers. We demonstrate that the link between these complementary characterization techniques is very beneficial to assess material quality, and so paving the way to effective ultrathin 2D material study and learning.