Nanomaterials and processes for advanced semiconductor CMOS devices

Resume : Developing and implementing next technology nodes is a complex task involving innovation in materials engineering, process development and device design. Metrology is now recognized as an important enabler within the development paths of novel technologies and also a crucial component for their manufacturing implementation. The gap between metrology for device and material development (lab based) versus manufacturing (lab based) has traditionally been very large as they were acting frequently on very different length scales (for instance blanket versus device analysis), with different response times and amount of data. The down scaling of devices into non-planar structures has led to physical phenomena which can only been seen in 3D-structures and confined volumes such that the lab based metrology is now pushed into dealing with device dimensions and expands rapidly into atomic scale metrology. (Fab) Metrology linked to manufacturing of next generation technologies also needs to address the specificity of nano-scaled devices and similarly requires a shift towards high spatial resolution analysis, be it that the volume and speed requirements interfere with some of the solution proposed in the lab. We will provide an overview of novel developments addressing atomic scale analysis in logic and memory devices as well as new approaches towards high spatial resolution analysis suitable for high volume analysis while matching the technology requirements.

Resume : In order to fabricate ultra-shallow junction (USJ) for 20nm IC node application, a low energy (400eV) ion implantation and a novel microwave annealing technique with two steps for the solid phase epitaxy regrowth and activation of boron dopants in silicon were used in this study. In the first step annealing, a 2.4 kWatt(~500℃) high power microwave annealing was used to re-growth the amorphous layer with PAI treatment of Ge (20keV @5e14 atoms/cm2) into crystal silicon. The activation energy (2.3 eV) to attain rapid lattice restoration for the solid phase epitaxy regrowth by microwave annealing is lower than that by the conventional RTP. In the second step annealing, since the crystalline silicon has high absorption efficiency to microwave, a 0.6 kWatt(~250℃) low power microwave annealing is able to activate implanted boron in silicon (400eV @1e15 atoms/cm2 ), and decrease the resistance to 436 ohm. / sq without diffusion. We have successfully demonstrated that the novel ultra low temperature microwave annealing technique is promising for improvement on P-MOS performance. The on/off current ratio (Ion/off) of the P-MOS is more than 2x106 (VDS = -0.05 V). The low resistance of 436 ohm./ sq after activating by 250℃ microwave annealing is reflected to the high performance of P-MOS with a lower S.S.(-92.59mV) ,and a high hole mobility27.5cm2/V-S.

Resume : Molecular monolayer doping (MLD) presents an alternative to achieve doping of silicon in a nondestructive way, and holds potential for realizing ultra-shallow junctions and doping of non-planar surfaces. Here, we report the mixing of dopant-containing alkenes with alkenes that lack this functionality, at various ratios to control the dopant concentration in the resulting monolayer and concomitantly the doping dose in the silicon substrate [1]. The mixed monolayers were grafted onto hydrogen-terminated silicon using well-established hydrosilylation chemistry. Contact angle measurements, X-ray photon spectroscopy (XPS) on the boron-containing monolayers, and Auger electron spectroscopy on the phosphorus-containing monolayers show clear trends as a function of the dopant-containing alkene concentration. Dynamic secondary ion mass spectroscopy (D-SIMS) and Van der Pauw resistance measurements on the in-diffused samples show an effective tuning of the doping concentration in silicon. [1] L. Ye, S.P. Pujari, H. Zuilhof, T. Kudernac, M.P. de Jong, W.G. van der Wiel and J. Huskens, accepted for publication in ACS Applied Materials & Interfaces.

Resume : Molecular doping of semiconductors is a rapidly growing area because it provides a simple, scalable and cost-effective alternative to standard fabrication methods and additionally allows conformality on structured surfaces. During this process the molecule chemically bonds to the target surface with a self-limiting process ruled by its steric properties. Thermal process performed after the formation of the self-assembled layer drives the diffusion of dopant atoms inside the substrate matrix. The technique allows the formation of n- or p- type doped Si, by properly selecting the precursor source [MATER SCI ENG B 178 (2013) 686], doping on structured surfaces [Phys. Stat. Sol. A 210 (2013) 1564] and fabrication of Si nanowire based solar cells [Sol. En. Mat. Sol. Cells 132 (2015) 118]. Most of the work on molecular doping lacks of information on the molecule / Si interface chemical properties, on the mechanisms of the molecule evolution during the coating and the diffusion step. Moreover it has so far been devoted to the molecules design to tune the final dopant dose and distribution. We present results on the interface characteristics and evolution, also in terms of mono- and multi-layers formation and on the doping features, such as junction depth, carrier dose and sheet resistance, carried out by fixing the dopant precursor and varying the coating conditions.

Resume : The advent of non-planar device architectures, along with device scaling, has created the need for a radically new, conformal and preferably non-destructive method for doping semiconductors. Molecular layer doping (MLD) has recently been shown to be an effective, chemical approach for doping semiconductor substrates and nanodevices, e.g. FinFETs, without causing crystal damage as seem with traditional ion-bombardment techniques. MLD comprises two steps: i) functionalisation of the semiconductor surface with a p- or n- dopant containing molecule and ii) thermal diffusion of the dopant atoms, by rapid thermal annealing, into the semiconductor. However, as electronic devices are scaled towards smaller dimensions, further optimisation of MLD processes are required, e.g. to achieve a carrier concentration >10^20 at/cm^3 at really shallow depths (< 20 nm). The depth to which dopants can be driven, and controlled, by thermal annealing has however proven to be a difficult task, particular in high mobility semiconductors such as Ge. To-date, there have only been a few reports of shallow doping by MLD in Si. This presentation describes the use of different surface functionalisation approaches, in particular the application of spacer molecules, and advanced annealing techniques to control the diffusion depth of dopants in Ge by MLD. AFM, XPS and ECV analysis of phosphorous-doped Ge substrates, as well as TEM and electrical measurements of Ge nanowire devices will be presented.

Resume : The influence of Al on the phase formation between Ni and Si(001) was investigated by altering the Al concentration and the Ni thickness. In a first series of samples, 20 nm Ni on a Si (001) substrate was alloyed between 0 and 50 at. % Al. The phase formation was examined during heating by sheet resistance and XRD. Small additions of Al (0- 28%) in the Ni layer result in a mono-silicide layer that is far more stable towards agglomeration. Polefigure measurements indicate that the axiotaxial texture of NiSi is less prominent and that the grain size is smaller when compared with silicides originating from pure Ni. When heated to higher temperatures, these samples form an epitaxial layer, identified as NiSi2. Without the addition of Al, NiSi2 is known to grow in two epitaxial orientations. When Al is added, the orientation defined by NiSi2(1-22)//Si(001) and NiSi2(1-10)//Si(101) is hindered, possibly causing a smoother interface with the Si substrate. Adding more than 30 at.% of Al results in a highly different phase formation where no NiSi formation could be observed. A second series of samples investigated the addition of Al for Ni films thinner than 10 nm. Ultrathin Ni layers are known to react directly into an epitaxial NiSi2 phase without first forming NiSi. When alloyed with Al, the critical thickness for this phenomenon to occur is elevated from 4-5 nm to 8 nm, indicating that the addition of Al is beneficial for the growth of epitaxial NiSi2.

Resume : Performance enhancement of MOSFETs is realized by introducing appropriate levels of strain in silicon. Stress in Si in various directions results in localized strain fields and affects the silicon piezoresistance coefficients. Tensile stress in a silicon channel increases electron mobility while compressive stress increases hole mobility. Uniaxial compressive strain is typically generated by embedding SiGe into the source/drain region of a device. Development of an accurate and reliable strain/stress characterization technique becomes extremely important for device simulation, design and manufacturing process monitoring and control of advanced MOSFETs. In this paper, stress in isolated Si1-xGex test pads and silicon lines and circles surrounded by Si1-xGex was characterized by a polychromator-based, very high resolution Raman system (WaferMasters MRS-300) as a function of pattern diameters, widths, and pitch. Three major spectral lines (457.9, 488.0 and 514.5 nm) from a multiwavelength Ar ion laser are used as the excitation source. Five patterned Si1-xGex/Si(100) wafers with nominal Ge content in the range of 15~35 at% were characterized. Nominal Si1-xGex layer thickness is ~40 nm. Stress of the Si circles surrounded by SiGe was negligible. For linear arrays with pattern size of 100~300 nm, the Si stress increased with increasing pitch size. For the linear arrays with 500 nm pitch and the blanket area, the Si stress was relatively small and independent of pitch.

Resume : We report on the investigation of electrically active defects at the interface between germanium and germanium oxide. Germanium is a promising channel material for high performance CMOS [1], provided the proper material is successfully implemented as gate oxide. In particular, the gate stack comprising a high-k oxide and a GeO2 insulating layer is one of the best options, in terms of scalability and density of interface traps (Dit) [2]. Still, at present the Ge/GeO2 interface is lagging behind the silicon counterpart, mainly due to traps that are not passivated by hydrogen anneal. In this regard, we previously identified the Ge dangling bond (DB) as an electron trap at the interface, by means of electrically detected magnetic resonance spectroscopy [3,4]. In this paper, we present an extensive investigation of Ge/GeO2/Al2O3 MOS capacitors by admittance spectroscopy, revealing the negative-U behavior of interface traps with transition levels about 0.1 eV above valence band edge. This result provides further insight into the reasons of the unsuccessful hydrogen passivation of the traps and the undetectability of Ge DBs by conventional electron spin resonance. [1] R. Pillarisetty, Nature 479, 324–8 (2011). [2] X. Yang et al., Appl. Phys. Lett. 105, 092101 (2014). [3] S. Baldovino, A. Molle, and M. Fanciulli, Appl. Phys. Lett. 93, 242105 (2008). [4] S. Paleari, S. Baldovino, A. Molle, and M. Fanciulli, Phys. Rev. Lett. 110, 206101 (2013).

Resume : The emergence of advanced semiconductor devices, like those based on silicon carbide (SiC) successfully contributes to developing applications for hostile environments. Due to outstanding SiC properties, such as wide band gap, low dielectric constant, high breakdown voltage, good thermal conductivity, chemical stability in reactive environments, SiC sensors are capable of operating properly at high temperatures and hostile environments. In this paper we investigate the temperature influence on the behavior of hydrogen sensors based on MOSiC capacitors which use Pd and Ni as catalytic gates. The structures were fabricated on n-type 4H-SiC Cree wafers, with an active epitaxial layer having a thickness of 7.9 μm, and doping of 2.07E16 cm¬¬¬-3. The oxide layer, with different thicknesses, varying from 10 to 50 nm was thermally grown. A chip structure with three different areas has been developed in order to obtain a sensor array for hydrogen detection. The sensor response, measured on a Pd MOSiC structure, shows an important temperature dependence up to 200°C. After this threshold, the sensitivity remains practically constant. This behavior can be associated with the presence of interface states, which affect sensor sensitivity at low temperatures. Over 200°C, the effect of interface states is diminished by the Fermi level shift into the SiC bandgap.

Resume : Germanium (Ge) is being actively considered by the semiconductor community as a mainstream material for nanoelectronic applications. Ge has advantageous materials properties; however, its dopant-defect interactions are less understood as compared to the mainstream material, silicon. The understanding of self- and dopant diffusion is essential to form well defined doped regions. Although p-type dopants such as boron exhibit limited diffusion, n-type dopants such as phosphorous, arsenic, and antimony diffuse quickly via vacancy-mediated diffusion mechanisms. In this presentation, experiments on self- and dopant diffusion in Ge are reviewed. Accurate modeling of the experimental profiles provides detailed information about the type and properties of native point defects in Ge and their impact in dopant diffusion. The results deduced from self- and dopant diffusion in Ge confirm the predictions of theoretical calculations. Overall a consistent picture on the diffusion mechanisms and on the properties of the native point defects is obtained that helps to develop efficient defect engineering strategies to restrain dopant diffusion in Ge and to enhance their electrical activation [1]. In contrast to recent results of Cowern et al. [2], no evidence on the existence of different forms of Ge self-interstitials with low and high formation entropies is found. [1] A. Chroneos and H. Bracht, Appl. Phys. Rev. 1, 011301 (2014). [2] N.E.B. Cowern et al., Phys. Rev. Lett. 110, 155501 (2013)

Resume : Experiments on the diffusion of boron (B) in germanium have been performed under equilibrium [1] and non-equilibrium conditions [2]. The equilibrium diffusion experiments provide a B diffusion activation enthalpy of 4.65 eV for temperatures between 800°C and 900°C that exceeds the activation enthalpy of self-diffusion by 1.5 eV. The high activation enthalpy of B diffusion is considered to indicate a Ge self-interstitial mediated diffusion rather than via vacancies [1]. This seems to be supported by B diffusion under non-equilibrium conditions established by irradiation [2,3]. Theoretical calculations [4] predict a repulsive interaction between substitutional B and vacancies showing that the activation enthalpy of B diffusion via vacancies will also exceed the activation enthalpy of self-diffusion. To clarify the mechanism of B diffusion in Ge we performed additional studies under equilibrium conditions to extend the temperature range and thus to determine the activation enthalpy of B diffusion more accurately. Moreover, the impact of doping on B diffusion is investigated to deduce the charge state of the mobile B species. Finally, the equilibrium diffusion of B is compared to its diffusion behavior under irradiation to deduce a consistent model of B diffusion in Ge. [1] S. Uppal et al., J. Appl. Phys. 96, 1376 (2004) [2] E. Bruno et al., Phys. Rev. B 80, 033204 (2009) [3] S. Schneider et al., Phys. Rev. B 87, 115202 (2013) [4] A. Chroneos, J. Appl. Phys. 107, 076102 (2010)

Resume : Germanium – well known as an important material option for high performance CMOS – has recently emerged as a remarkable test-bed for new concepts of defects and diffusion. Two years ago a study of B diffusion in Ge revealed the existence of a new class of mobile high-entropy defects [1]. Related to, but distinct from, a previous concept proposed by Seeger and Chik, the structure was proposed to be an amorphous pocket of nanoscale dimensions, or ‘morph’. This idea – and even the very existence of high-entropy mobile defects – has sparked disagreement [2]. Nevertheless, a detailed comparison of temperature-dependent data on radiation-enhanced diffusion of B and host atoms in Ge confirms that, in this system, interstitial-mediated diffusion mechanisms of B and especially host atoms at high temperature involve unusually high entropies (in the range of several tens of k). The talk shows how a surprising depth of detail can be obtained about the way the interacting defects evolve during self-diffusion and the microscopic process of displacement and migration of dopant atoms. These insights confirm the morph concept, placing it on a comparable footing with the better known compact point defects. Implications for other systems, including silicon, are discussed with reference to recent research reports. [1] N. E. B. Cowern, S. Simdyankin, C. Ahn, N. S. Bennett, J. P. Goss, J.-M. Hartmann, a. Pakfar, S. Hamm, J. Valentin, E. Napolitani, D. De Salvador, E. Bruno, and S. Mirabella, Phys. Rev. Lett. 110, 155501 (2013). [2] A. Chroneos and H. Bracht, Appl. Phys. Rev. 1, 011301 (2014)

Resume : The scaling of CMOS technology over the past four decades has revolutionized our society. The microelectronic industry is now facing some serious challenges in shrinking those dimensions beyond the 14nm node. Pure geometrical scaling does not bring anymore the expected benefits in terms of performance and power consumption. In the past decade, however, the industry gradually moved to innovation-driven scaling and brought to the market chips based on strained silicon, silicon-on-insulator, high-k/metal gate technology, tri-gate devices… This trend will continue with the move to high-mobility channel materials such as SiGe and III-V compound semiconductors that will need to be co-integrated on the same platform. Numerous challenges still have to be tackled in order to turn the high-mobility CMOS concept into an industrial solution. In this contribution, we will review how direct wafer bonding has enabled the integration of high-quality InGaAs-on-insulator on large-scale Si substrates [1,2,3]. Key process modules for the fabrication of CMOS-compatible self-aligned InGaAs MOSFETs will be addressed [4,5]. Finally, hybrid III-V/SiGe dual-channel CMOS inverters will be presented [6,7]. [1] L. Czornomaz et al., IEDM (2012), [2] N. Daix et al., APL Mat 2, 086104 (2014), [3] E. Uccelli et al., SSDM (2014), ), [4] L. Czornomaz, et al., ESSDERC (2013), [5] V. Djara et al., EuroSOI-ULIS (2015), [6] L. Czornomaz et al., IEDM (2013), [7] L. Czornomaz et al., SNW (2014)

Resume : GaN is an important wide-gap semiconductor that is an essential component in blue light emitting diodes. Producing p-type layers has proven to be a major challenge, which has only been overcome by doping with large concentrations of Mg. Exactly how doping affects the minority charge carrier concentration remains a controversial issue, with many theoretical studies producing contradicting results. We present results of calculations based on a hybrid quantum mechanical/molecular mechanical embedded cluster approach to modelling defect formation associated with divalent metal dopants in GaN, with a particular focus on the technologically crucial case of Mg doping. As this approach gives a consistent description of polarisation and provides access to a well-defined reference, accurate and unambiguous defect levels are determined. From our calculations we show that isolated Mg atoms act as very deep traps for holes, which explains the lack of p-type activity in lightly doped samples. We attribute native n-type conductivity to N vacancies, which act as shallow donors. A large amount of experimentally determined optical data can be assigned to these N vacancies, which are charge-compensating defects for divalent dopant incorporation. Our calculated defect ionisation levels associated with the dopants are in excellent agreement with a wide range of experimental data.

Resume : Modern techniques, such as ultra-fast laser annealing, have been proposed for the activation of ion implanted dopants (e.g. boron) in very thin layers near the silicon surface, without harming the underlying buried device layers, which is of critical importance for the fabrication of 3D integrated devices. These annealing treatments produce high temperatures and introduce stress in very localized regions of the substrate in the nanosecond regime. We have studied the early stages of self-interstitial clustering in silicon in such conditions of high temperature and stress using molecular dynamics simulation techniques. We have generated silicon samples of 200000 atoms where we introduced a 0.5% extra concentration of self-interstitials. Then samples were annealed at several temperatures and external pressures, both compressive and tensile. During the simulations we observed the formation of interstitial clusters with different atomic structures, ranging from spherical and amorphous-like clusters, to highly ordered extended configurations such as {311} defects, {111} rod-like defects and dislocation loops, and {100} planar defects. The particular morphology of formed interstitial clusters is found to be related to the applied external pressure and the annealing temperature, as it is observed in the experiments. From the molecular dynamics simulations we will analyze the atomic mechanisms leading to the formation of different defects.

Resume : SiGe alloys are used in many types of electronic devices. For upcoming FinFET technologies, there is interest in the use of SiGe heterostructures in the complete molefraction range (0% - 100% Ge atoms). For high germanium molefraction and small device dimensions, inter-diffusion of Si and Ge atoms can lead to critical changes in the distribution of Si and Ge atoms, impacting channel strain and carrier mobility. A process model for Si-Ge interdiffusion has been developed which covers the needs for actual device fabrication processes. Interdiffusion is understood to be correlated with the diffusion of vacancies, interstitials, and dopant-defect pairs. We consider the impact of non-equilibrium point defect concentrations (such as interstitial super-saturation after ion implantation), the impact of compressive or tensile strain, and a twofold impact of doping: First, doping determines the local electron concentration and thereby the abundance of charged point defects, and second, the diffusion of dopant-defect pairs can contribute to the interdiffusion of Si and Ge atoms. The model covers the full range of possible Ge molefractions (0-100%). For undoped SiGe, it has been calibrated against a broad range of published experimental data for radio-tracer diffusion in SiGe and for interdiffusion in biaxially strained SiGe heterostructures grown on Si, stress-relaxed SiGe, or Ge. The extensions for doped SiGe are presented with a reference to few interdiffusion data for heavily doped SiGe heterostructures. Finally, the model has been consistently integrated into a set of models for the continuum process simulation of point defects and dopants in pure Si, SiGe, and pure Ge, in Sentaurus Process.

Resume : The extremely high 2DHG low temperature mobility of over 1.3*10^6 cm2/Vs (Ps=2.9?10^11 cm-2) [1-4] and very low hole effective mass (0.060 ± 0.001)mo determined from Shubnikov-de Haas oscillations has enabled the fractional quantum Hall effect (FQHE) to be observed for the first time in the ranges of magnetic fields up to 35T and temperatures 25mK

Resume : Among all III-V nanowires (NWs), InAs NW is of great interest due to its high electron mobility and infrared bandgap. One of the main challenges for its application is to get controlled crystal phase in epitaxy, which entails the control of (111) planar defects (PDs) randomly distributed along the NW axial direction. For widely used vapor-liquid-solid (VLS) method, there were great progresses in PD control recently. Unfortunately, the VLS technique is not an optimum path for large scale NW device fabrication. Instead, selective area growth (SAG) is a method more desirable allowing placement control and avoiding metal impurities. But when using SAG, PD control is much more challenging. To our knowledge, InP NW is the only one that could be obtained in pure crystal phase by this method in the III-V NWs family till now. We report here the wurtzite (WZ) phase InAs NWs SAG on a patterned Si (111) substrate using a metal-organic vapor phase epitaxy (MOVPE) system. PD frequency in InAs NW is not influenced by NW diameter in our studied range (30-350nm), but can be controlled by basic growth parameters. WZ InAs NWs (hexagonality = 93%) with uniform diameter of about 220nm were obtained under the condition of high growth temperature, low V/III ratio and low growth rate. Because there is no liquid phase involved, this study also provides an important input to understand the mechanism of crystal phase switching during NW growth in a simple picture.

Resume : Closing remarks