Alternative semiconductor integration in Si microelectronics: materials, techniques & app

Resume : Monolithic integration of III-V semiconductors epitaxially grown on Si substrate have been attracting much attention as building blocks for next-generation electronics and photonics due to their potential intrinsic properties. We report here on the growth of InP and related compounds on STI patterned Si wafers by Selective Area Metal-Organic Vapor Phase Epitaxy. Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8% between the Si substrate and high mobility III-V compounds. We investigated the fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. As a conclusion, this study of III-V selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on (001) oriented Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is original and obviously confirm the potential of this heterogeneous integration option for high mobility logic devices, and photonic applications on a common Si platform.

Resume : Heterogeneous integration of compound semiconductors on silicon is the Holy Grail for many technologies that are critical for the society today. Low power CMOS digital circuits, high performance wireless analog systems, low cost integrated photonic circuits – to name a few – would greatly benefit from such an innovation. Moreover, most of these applications would benefit from having the compound semiconductor layer on top of an insulator. Many approaches have been considered, taking advantage of the defect reduction in thick buffers using wafer bonding, or of defect filtering in nanoepitaxial concepts such as epitaxial lateral overgrowth or aspect ratio trapping. We report here on the demonstration of the integration of high-quality InGaAs or InP on insulator on Si substrates, using a novel concept named Confined Epitaxial Lateral Overgrowth (CELO). This method, based on selective epitaxy, only requires the use of standard large-area silicon substrates and typical CMOS processes. Its key feature is to rely on a geometrical filtering of defects, using changes in the growth direction rather than in the dimensions of the grown crystal. It enables the fabrication of “on-insulator” structures starting from both bulk and SOI Si wafers. The InGaAs and InP epitaxial structures are characterized by a very low defectivity. Such substrates can fulfill the requirements of advanced CMOS nodes, as exemplified by the demonstration of short channel, gate-first, self-aligned FinFETs with excellent electrical characteristics. The device metrics are comparable to state-of-the-art InGaAs MOSFETs on Si, highlighting the potential of our approach.

Resume : The integration of III-V materials having high carrier mobility and direct band gap on silicon substrates is an important issue for future microelectronic and optoelectronic applications, and has received renewed interest in recent years. However, the epitaxy of III-V materials on Si presents many difficulties, mainly because of the large difference in lattice parameter (>4%) and the polar/non-polar character of layer/substrate interface, thereby generating numerous structural defects such as dislocations and antiphase domain boundaries (APBs) in the epitaxial layers. We will focus on our latest achievements in the growth and properties of III-As heterostructures by metal organic chemical vapor deposition on (100)-oriented Si substrates, and also on patterned substrates. The optimization of growth parameters has enabled us to obtain thin GaAs epitaxial layers on blanket Si(100) substrates free of APBs. Room temperature µPhotoluminescence and low temperature cathodoluminescence results obtained on these layers will be presented, as well as their electronic properties obtained by Hall effect measurements. Also, the selective area growth in oxide trenches provides layers of high structural and optical quality near the top of cavities, by blocking most of dislocations in the oxide walls. The physicochemical characterization of these 3D structures obtained by ToF-SIMS, in correlation with their optical properties, will be presented. The results open the path for the integration of III-As based materials on a CMOS Si platform.

Resume : The interest in the integration of GaAs on Si is becoming stronger each year and is guided by applications in highly active areas such as silicon-based microelectronics technologies or photovoltaic. Significant improvements have been reported for many years, thanks to selective area epitaxy of GaAs on Si substrates patterned with dielectric films. However, these layers are inappropriate for applications involving electronic transport between GaAs and Si at a large scale. To overcome these problems we have developed a technique based on the epitaxial lateral overgrowth (ELO) of micrometer scale GaAs crystals on a 0.6 nm thick SiO2 layer from nanoscale Si seeds. The nucleation from small width openings enables to avoid the emission of misfit dislocations and the formation of antiphase domains. Besides, as the thickness of the oxide interfacial layer is sufficiently thin, a tunneling current may occur and lead to interfacial conductivity between GaAs and Si. Transmission electron microscopy analyses indicate that GaAs islands are defect free and perfectly integrated with the Si substrate. Additional measurements by confocal Raman microscopy and ?-PL, confirm the good quality of epitaxial GaAs layer. Finally, conductive AFM and EBIC I-V measurements were also performed and show that the heterojunction between GaAs and Si through the thin SiO2 interfacial layer is highly conductive. These different results will be presented and discussed during the communication.

Resume : The integration of III-Vs on a silicon platform would bring together the better of two worlds: the high integration density, high volume, mainstream silicon technology with the high frequency, direct bandgap and wide flavor of III-V alloys, greatly extending the functionalities of tomorrow’s microchips. To that end, we have first of all grown on standard 300 mm Si(001) substrates rather thick (~ 1 µm) Ge layers in a group-IV RPCVD equipment (in order to accommodate the 4 % lattice mismatch between Si and GaAs). This will save costly III-V organometallic precursors and yield higher crystalline quality layers. We have then grown in an Applied Materials MOCVD tool ~ 300 nm thick GaAs layers on top of those Ge buffers. We have explored the impact of temperature, pressure, growth rate and V/III gas phase ratio on the nucleation of GaAs on Ge. With optimized growth conditions, we have obtained GaAs layers that were uniform (<2% standard deviation over the whole 300 mm wafer), smooth (<1 nm RMS AFM 5x5 µm2 roughness), nearly Anti-Phase Boundaries - free and with a threading dislocation density of a few 107 cm-2 only. Photo- and cathodo-luminescence measurements have been performed on those GaAs layers, together with high resolution X-ray diffraction. The GaAs layers were slightly tensile strained, n-type doped (diffusion of Ge atoms) and of high optical quality. A GaAs on Ge on Si approach thus seems suitable for the integration of As- and P-based III-Vs on large diameter substrates

Resume : In this communication, we report on the development of an (In)GaP platform monolithically integrated on silicon for photonics and energy. The realization of a low defect density GaP/Si(001) platform is first presented with growth developments and associated structural characterizations (synchrotron and lab XRD setup, STM and TEM): the main result being the early annihilation of antiphase domains around 10nm of the GaP/Si interface.[1] As an illustration of the GaP/Si platform potential, three optical devices integrated on silicon will be presented: (i) a GaAsPN/GaP/Si photovoltaic solar cell for the development of a tandem architecture on silicon,[2] (ii) an electrically-driven GaAsPN/GaP/Si light emitting diode for further laser developments and its integration with CMOS and (iii) a GaP/Si microdisk which could be potentially used for non-linear conversion and lasing. Finally, the advantages provided by the addition of indium in GaP will be discussed in terms of bandgap engineering, and carrier mobility.[3] Preliminary results toward the development of an InGaP/SiGe/Si platform will be presented. [1] Y. Wang et al., J. Appl. Cryst., (in press 2015). [2] S. Ilahi et al., Sol. Energy Mater. Sol. Cells (in press 2015). [3] O. Skibitzki et al., J. Appl. Phys. 115, 103501 (2014).

Resume : In this work, we investigate the growth of GaN High Electron Mobility Transistors (HEMTs) for monolithic integration with Silicon CMOS circuits. The present CMOS-first approach relies on the ammonia-MBE growth of AlGaN/GaN heterostructures on masked Silicon substrates. The presence of CMOS devices on the wafer is a challenge that has been addressed by reducing the maximum growth temperature of (Al,Ga)N buffer materials from 920°C to 830°C without any degradation of the GaN crystal quality as assessed by X-ray diffraction. This is a noticeable difference compared to the MOCVD technique with materials grown at temperatures superior to 1000°C. In addition, we develop dielectric stacks able to withstand the large stress arising from the growth process and to eliminate the delamination issue due to the large difference in thermal expansion coefficient between GaN and Silicon. Hall effect measurements confirm the quality of the epilayers. Capacitance-voltage measurements show that the HEMT epitaxial structures provide a capacitance plateau with a sharp pinch-off behavior attesting the absence of significant contaminations. More, transistors show output characteristics in agreement with the previously assessed transport properties and reduced electrical leakage in spite of the presence of a dielectric mask on the Silicon substrate. This is a progress compared to previous local area ammonia-MBE works where buffer contamination had to be compensated with impurities like Carbon.

Resume : Integration of different materials, such as GaAs or Ge, on Si via heteroepitaxy is nowadays a key step involved in the fabrication of a multitude of devices, some already in the market. However, full control over the different, sometimes competing phenomena taking place during deposition [1] has yet to be reached. Simulations can be precious in limiting the growth-parameter space to be sampled in actual experiments when searching for the desired system quality and morphology. In this work we present a continuum approach able to tackle heteroepitaxy while matching typical experimental sizes and time scales. A convenient and general description of surface-energy anisotropy is introduced [2] and several illustrative applications to semiconductors are described, exploiting both Phase-Field and sharp-interface approaches. Successful comparison with experiments is demonstrated for qualitatively different systems. We also discuss how to simultaneously tackle elastic and plastic relaxation. In particular, we show how the stress field associated with an assigned distribution of misfit dislocations can be computed on the fly, its contribution to the surface chemical potential deeply influencing the growth mode and/or the morphology of the growing front. [1] F. Montalenti, D. Scopece, and Leo Miglio, Comptes Rendus Physique 14 (7), 542-552 (2013). [2] M. Salvalaglio , R. Backofen , R. Bergamaschini , F. Montalenti , and Axel Voigt, Cryst. Growth Des. (2015); (DOI:10.1021/acs.cgd.5b00165)

Resume : X-ray diffraction plays an important role in the analysis of strain, texture and epitaxial relation. Traditionally x-ray diffraction is considered as a method with poor spatial resolution yielding only spatial averages as useful results. Very recent developments in the use of highly focused beams produced on the most advanced synchrotron sources show however a great and rapidly developing potential of diffraction imaging techniques. At the ESRF Grenoble, ID01 is the beamline specialized on nanodiffraction imaging using scanning probe- and full-field techniques. Offering scanning diffraction microscopy at 100Hz with 100nm focused x-ray beams [1], full field x-ray diffraction microscopy using compound refractive lenses [2] and coherent beams for coherent diffractive imaging applications [3] we can supply a vast spectrum of techniques for high resolution strain imaging. Brought to maturity during the first phase of the ESRF upgrade these techniques allow for strain and texture imaging in thin films with a spatial resolution of 100 nm and strain sensitivity of =a/a<10-5 . The talk will give an overview on the state of the art of the nano diffraction imaging techniques readily available at ID01 and their typical field of applications today and in the near future. 1] G. A. Chahine, M.H. Zoellner, M-I. Richard, S. Guha, C. Reich, P. Zaumseil, G. Capellini, T. Schroeder and T. U. Schülli, Applied Physics Letters, 106, 071902 (2015). [2] J. Hilhorst, F. Marschall, T.N. Tran Thi, A. Last and T. U. Schulli, J. Appl. Cryst. 47, 1882-1888. (2014). [3] S. T. Haag, M-I. Richard, U. Welzel, V. Favre-Nicolin, O. Balmes, G. Richter, E. Mittemeijer and O. Thomas, Nano Lett., 13 (5), 1883–1889 (2013)

Resume : Silicon photonics has been aggressively pursued in the last two decades as an integrated platform to merge optics and electronics on the same chip. However, not all photonic functionalities can be conveniently realized on silicon, e.g., lasers. Furthermore, on some of the functionalities that can be realized, the performance of the devices are not as great as those on other platforms. For instance, silicon lacks electrooptic effect for optical modulation. Alternatively, the free-carrier plasma effect has been exploited to realize optical modulators. However, such silicon optical modulators are not well-poised for high-performance optical interconnect applications due to their low extinction ratio. The traditional lithium niobate electrooptic modulators, on the other hand, have higher performance in terms of extinction ratio and very high modulation bandwidth, but suffer from large footprint, high power, difficulty of etching to form ridge waveguides and lack of integrability with silicon photonics. To address these shortcomings, submicron thin films of lithium niobate are heterogeneously integrated onto oxidized silicon substrates. To form optical waveguides, the lithium niobate thin films are loaded with index-matched materials (e.g., Ta2O5 dielectric ?or Ge23Sb7S70 chalcogenide glass). Strongly confined single-mode lithium-niobate-on-silicon microring modulators with grating couplers, and Mach-Zehnder modulators in the telecommunication C band (~ 1550 nm wavelength) are accordingly demonstrated. This heterogeneous platform on silicon substrates yields a significant improvement in extinction ratio over all-silicon modulators, and maintains a device footprint much smaller than conventional lithium niobate modulators. This is a key step to enabling high-performance dense on-chip integration, a key requirement for components of short reach optical interconnects, and higher-order advanced modulation schemes.

Resume : Barium titanate (BTO) is a promising example for the successful integration of an electro-optical (EO) material with a strong Pockels coefficient on silicon. Active devices utilizing the EO effect in BTO have been demonstrated showing that it can be used for EO modulation in silicon photonics. However, the demonstrated devices suffer from high optical propagation losses (44 dB/cm), which limits the performance compared to state of the art silicon photonics devices (<5 dB/cm). We report on a systematic investigation of the origin of the propagation losses in hybrid BTO/silicon waveguides: SiO2-strip-loaded waveguides fabricated on BTO layers deposited on SOI (silicon-on-insulator) substrates by molecular-beam epitaxy showed no significant absorption at a wavelength of 1550 nm. However, propagation losses increased to ~20 dB/cm in Si/BTO/SOI slot waveguide structures. Such structures are required to enhance the optical confinement in the BTO layer in active devices. We could attribute the higher propagation losses to absorption in the BTO layer induced by the reducing atmosphere during integration of the upper silicon layer. Post-deposition annealing in different gas environments confirmed this observation. Strongly oxidizing environments can be applied to lower the propagation losses to <10 dB/cm, comparable to current silicon photonics technology. Our results in obtaining low-loss BTO/Si hybrid waveguides represent a major step towards a novel integrated photonics platform.

Resume : Crystalline oxide buffer layers permit the growth of functional complex oxides on silicon with properties close to those of films on perovskites. I will review our progress on the integration of ferromagnetic CoFe2O4 (CFO) and ferroelectric BaTiO3 (BTO). Ferrimagnetic CFO was grown epitaxially on Si(001) and Si(111) buffered with yttria-stabilized zirconia and bixbyte (Sc2O3 and Y2O3), respectively. In the latter case, where the lattice mismatch is huge, we discuss on the epitaxial mechanisms. The stability of the interface between the used buffer layers and silicon is compared. Ferroelectric BTO was integrated on Si(001) using a LaNiO3/CeO2/YSZ buffer layer that induces compressive epitaxial stress favoring c-orientation with high ferroelectric polarization along the out-of-plane direction. The ferroelectric properties, including polarization loops and fatigue measurements, of BTO films and CFO/BTO bilayers are discussed.

Resume : Resistive Random Access Memory (RRAM) devices based on resistive switching in hafnium oxide is being investigated extensively as emerging embedded nonvolatile memories. Oxygen engineering in hafnium oxide (HfO2) thin films has been achieved using strongly oxygen deficient growth parameters, stabilizing oxygen vacancy concentrations far beyond the thermodynamical equilibrium. It was found that the conductivity of hafnium oxide grown on c-cut sapphire substrates could be tuned in a wide range by varying the oxygen flow and undergoes a metal-insulator transition1. Thin films of hafnium oxide grown on epitaxial TiN(001)/Si(001) substrates with thicknesses of 20 nm crystallize in a monoclinic symmetry (m-HfO2) at higher oxidation conditions, whereas the oxygen deficient hafnium oxide films showed an oxygen vacancy stabilized tetragonal like phase of hafnium oxide (t-HfO2-x)2. A large concentration of oxygen vacancies lead to a defect band at the Fermi-level as observed by XPS. The electrical switching measurements show that the forming voltage is suppressed for oxygen deficient films paving the way for low power devices in future2. Our study suggests that the combination of oxygen deficient and stoichiometric layers of hafnium oxide with varying thicknesses can lead to forming free devices. [1] E. Hildebrandt et. al. Appl. Phys. Lett. 99, 112902 (2011). [2] S. U. Sharath et al. Appl. Phys. Lett. 104, 063502 (2014); Appl. Phys. Lett. 105, 073505 (2014).

Resume : The combination of standard wafer-scale semiconductor processing with the properties of functional oxides opens up to innovative and more efficient devices with high value applications which can be produced at large scale. In this direction, the present work used the main strategies to monolithically integrate functional oxide thin films and nanostructures on silicon: the chemical solution deposition approach (CSD) [1] and the advanced physical vapor deposition techniques such as oxide molecular beam epitaxy (MBE). Special emphasis will be placed on oxide thin films epitaxially grown on silicon using the combination of Polymer Assisted Deposition (PAD) and MBE [2]. Several examples will be presented, with a particular stress on the control of interfaces and crystallization mechanisms on epitaxial perovskite oxide thin films (La0.7Sr0.3MnO3, SrTiO3, BaTiO3…) and nanostructured piezoelectric quartz thin films on silicon [3]. This work enlightens on the potential of nanostructured oxide thin films and the combination of both chemical and physical elaboration techniques for novel oxide-based integrated devices. [1] A. Carretero-Genevrier et al. Nanoscale, 20, 892-897. (2014). [2] J.M. Vila-Fungueiriño et al. Frontiers in Physics, doi : 10.3389/fphy.2015.00038. (2015). [3] A. Carretero-Genevrier et al. Science, 20, 892-897. (2013).

Resume : Pyroelectric materials which couple a change in temperature to a change in electrical polarization offer possible conversion between thermal energy and electric energy [1]. They can thus be integrated in microelectronic devices, without the necessity to maintain thermal gradients like thermoelectric materials, i) for thermal energy harvesting (via the direct pyroelectric effect), and ii) for cooling applications (via the converse pyroelectric effect, so-called electrocaloric). According to the structural dependence of properties, single-crystalline pyroelectric films can provide an enhanced conversion energy efficiency with respect to bulk or polycrystalline materials [2]. In this communication, we will present the pyroelectric properties of epitaxial Pb(Zr0.52Ti0.48)O3 films grown by sol-gel process on SrTiO3(001) and buffered Si(001) substrates. In particular, we will show the impact of structural properties (domains orientation tuned by thermal mismatch) on the intrinsic pyroelectric coefficients and electrocaloric properties. Intrinsic pyroelectric coefficient can reach -450 µC.m-2.K-1 in c-oriented films. The corresponding harvested pyroelectric energy can be beyond 10 mJ.cm-3 per cycle for temperature variations of 10°C, and temperature changes of more than 10°C can be reached close to room temperature, that can address cooling applications in microelectronic devices. [1] S.B. Lang, Phys. Today 58, 31 (2005) [2] G. Sebald et al., Smart Mater. Struct. 18, (2009)

Resume : Now a days, transistors made by Ge incorporated with high-k dielectrics is the good replacement for the Si transistors to serve the scaling requirement of the 22nm technology node and beyond. We have studied the electrical properties of the HfO2 oxide deposited by atomic layer deposition (ALD) on in situ nitride passivated Ge substrate. The deposited films were annealed at 400 ºC for 2 minutes in N2 ambient by using rapid thermal annealing system (AET RX6 Model). The X-ray Photoelectron spectroscopy (XPS) result confirms the formation of GeOxNy over the germanium. The Hf 4f core level spectrum confirms the oxidation state of hafnium with doublet separation energy of 1.5ev. AFM showed the smooth surface morphology of the film. The GeON layer has the thickness of 2.85 Å measured with the help of spectroscopic elipsometry. The thickness of the HfO2/GeON stack was 5.6 nm. The Pt/Ti metal electrodes were deposited by electron beam evaporation system through shadow mask and back substrate contact was formed by depositing Aluminium using thermal evaporator. The electrical study was done by analysing capacitance voltage and also the current voltage measurements. The effective charge density Qeff calculated at 1MHz frequency was 2.11×1012 cm-2. Interface trap density Dit was calculated using Hill-Colemann technique and determined to be 3.00×1012 cm-2 eV-1. Also the effect of post deposition annealing was studied on the electrical properties of the Pt/Ti/HfO2/GeON/Ge devices.

Resume : We investigated the chemical states of sulfur embedded in atomic-layer-deposited (ALD) HfO2 thin films by annealing under H2S gas, using S K-edge X-ray absorption spectroscopy (XAS). Comparative studies of the H2S treatments prior to and after the HfO2 ALD on Ge substrates revealed that the valences of the S-ions were mostly -2 at the Ge/HfO2 interface, while they were mostly +6 in the HfO2 layers. The dominance of S2- at the interface can be easily understood as a consequence of filling of defects or formation of bonding toward Ge or HfO2, locally forming GeSx or HfO2-ySy, respectively, to passivate the interface. On the other hand, the prevalence of S6+ in the oxide layers is unexpected. Most plausibly, the huge valence originates from sulfate (SO4^2-) ions, implying that certain sulfates of HfO2-z(SO4)z are formed locally in the oxide layers. We observed that the leakage current density in the post-deposition-treated film is lower than that in the pre-deposition-treated one. This suggests that the sulfate ions, though their concentration might be low, can appreciably lower the defect density in the ALD HfO2 films.

Resume : We present recent results on inter-subband (ISB) light absorption and carrier relaxation dynamics in n-type s-Ge/Ge0.82Si0.18 multi quantum wells (MQW) grown on SiGe/Si(001) virtual substrates. By using FTIR Spectroscopy and pump and probe measurements, we evidenced ISB absorption occurring in the 15-45 meV spectral region (3-10 THz) and featuring line-widths of =2 meV up to 300K. The experimental data were analyzed relying on a theoretical model taking into account scattering processes due to interface roughness, spatial distribution and density of ionized donors, phonons, and extended defects. We predict that line-width <1 meV and coherence time c>1 ps can be achieved. Non radiative relaxation times R>30 ps have been measured up to 130K. Moreover, we have fabricated structures based on a three-level coupled-MQW design and measured the relaxation time  using a tunable-FEL emitting at photon energies matching the two ISB transition energies 01 and 02. We found that 10 relaxation is faster than 21, featuring a relatively high relaxation time ratio of 10/21 ≈ 0.5. Based on these results, we calculated that the optical transparency threshold can be attainted for optical power density of 30 kWcm-2. This threshold value could be further reduced by an optimization of the mode confinement in a suitable optical cavity. Our results demonstrate that n-type s-Ge/Ge0.82Si0.18 MQW are a promising route towards silicon-based on-chip emitters in the THz range.

Resume : The insertion of O monolayers (MLs) into the Si channel has recently been shown to improve both electron and hole mobility in CMOS devices (Xu, IEDM 2012; Xu, IEEE TED 2014) with a compatible Si fabrication processes for the integration. The initial explanation for the observed effect was the separation of carrier wavefunction distributions due to the O-related band edge shift resulting in reduced scattering rates. To shed some light on Si-O superlattices (SLs) electronic structure, we used internal photoemission (IPE) of electrons, which allowed a straightforward probing of electron density of states and of the band bending inside the Si-O SL region. SLs made of 1, 2 or 5 periods of one ML of O in between 25, 15, 7, 3 or ~1 nm thick Si layers were studied by using IPE from these SLs into 20-nm thick Al2O3 film deposited on top of the SL. We observed the reduction of direct optical transition intensity in Si-O SLs by decreasing the thickness of SL periods to 1 nm, indicating the Si crystalline structure distortion inside the SL. Any change of the field dependence of IPE spectral threshold indicates no effect of O MLs on the valence band (VB) energy or on the field-induced band bending inside SL w.r.t. bulk Si. Thus, we may conclude that there is no evidence of VB edge profile modification which is the pre-requisite for carrier wavefunction redistribution. The reported enhanced mobility may be explained by the effect of O – induced stress in Si, which affects the carriers effective mass. Further, electron spin resonance indicates the absence of additional Si dangling bonds in the Si-O SL with the sensitivity of 10^11 cm-2. These findings suggest that Si-O SLs enhance the carrier mobility by inducing stress in the Si channel without creating additional harmful defects.

Resume : The observation of lasing action in GeSn opens a new path for monolithic integration of electronics and photonics based on Si. In this context, the incorporation of Si into GeSn and epitaxial growth of GeSn/(Si)Ge(Sn) heterostructures are essential for electrically pumped optoelectronic devices. We will discuss the electronic band structure calculations for a variety of Group IV heterostructures, including e.g. SiGeSn claddings and GeSn active layers with type I band alignment suitable for light emitting diodes and electrically pumped laser diodes. Here, Si and Sn concentrations up to 14 at.% in the cladding layer offer an effective carrier confinement with band offsets of a few hundred meV with respect to the active layer. Epitaxial growth of direct GeSn and indirect SiGeSn layers using an industry compatible AIXTRON reduced pressure CVD reactor with showerhead technology will be presented. Si2H6, Ge2H6 and SnCl4 were employed as precursors, while B2H6 and PH3 allow in-situ doping of the grown layers. Single epilayers and multi quantum well structures have been analyzed using RBS, TEM and X-Ray diffraction showing excellent layer morphology and high Sn substitutionality. Optical characterization was performed via photoluminescence and electroluminescence on both layers and pin diodes. Room temperature electroluminescence is observed for small current densities of about 50 Acm-². This demonstrates the potential of Group IV heterostructure for optoelectronics.

Resume : Although silicon CMOS has been the process of choice for many uses in optoelectronic industry, its use for IR sensitive optoelectronic devices is limited to below ~1100 nm by the 1.11 eV band-gap of silicon. Extending the optical sensitivity range of silicon devices up to several microns, while maintaining good sensor responsivity, short rise and fall times, and maintaining the CMOS process compatibility, would be of great importance for possible telecom or other optoelectronic uses. Heterojunction interfaces between organic thin films and silicon often show synergetic advantages regarding certain properties. We present our work on optoelectronic devices based on heterojunctions of silicon and organic thin films of hydrogen-bonded pigment tyrian purple (6,6′-dibromoindigo) formed by vacuum evaporation. Tyrian purple is an ambipolar organic semiconductor with an optical band-gap of 1,9 eV and electron and hole mobilities of 0,4 cm2/Vs, which forms rectifying junctions with p-doped silicon. Even though the band-gap of both materials in the heterojunction is relatively high, our devices show sub silicon-bandgap IR sensitivity up to 2500 nm with responsivity of ~5 mA/W in the telecom C-band. Finally, we show that micro- and nano-structuring of silicon substrates prior to vacuum evaporation of organic layer significantly improves the responsivity of hybrid silicon-organic photodiodes.