Alternative semiconductor integration in Si microelectronics

Resume : Detailed understanding of Si preparation and formation of polar-on-nonpolar interfaces is a prerequisite for heteroepitaxial integration of III-V semiconductors on Si. By varying preparation conditions in metalorganic vapor phase epitaxy (MOVPE) ambient, we can choose between energetically and kinetically driven Si(100) step formation, which results in majority domains of monohydride-terminated Si dimers oriented either parallel or perpendicular to the step edges [1]. The sublattice orientation of subsequently grown single-domain heteroepitaxial GaP films depends on the domain type of the Si substrate surface. In an abrupt interface model, the correlation of the orientation of P dimers and Si dimers, respectively, by in situ reflection anisotropy spectroscopy (RAS) favors Si-P bonds at the heterointerface which contradicts literature [2]. Also ab initio density functional theory (DFT) calculations show that Si-P bonds are energetically favored over Si-Ga bonds for P-rich growth conditions at abrupt interfaces. In thermodynamic equilibrium, the energetically most favorable interface is compensated with an intermixed interfacial layer. In situ RAS, however, reveals that the GaP sublattice orientation depends on the P chemical potential during nucleation which agrees with a kinetically limited formation of abrupt interfaces. [1] S. Brückner et al., PRB 86:195310 (2012); New J. Phys. 15:113049 (2013). [2] Beyer et al. JAP 111:083534 (2012).

Resume : Replacing silicon with high-mobility channel materials such as InGaAs will be surely the next evolution of MOSFET devices. Alternative materials such as High- dielectrics and metal gates have already been successfully introduced. InGaAs based channels hold the promise of circuits operating at lower Vdd and hence consuming low power as the dynamic power roughly scales as V2dd. Two different strategies for integrating As based compounds as MOSFET channels are actually foreseen: fully depleted III-V/On Insulator or FinFET. This integration still faces many challenges like direct III-V epitaxy on Si, channel/high k interface control, and contact resistance. We focus on the direct growth of As compounds on Si(100) 300 mm substrates. GaAs and InGaAs layers are grown by an Applied Materials MOCVD tool. TMIn, TMGa and TMAl are used as group III elemental precursors whereas TBAs is used as group V elemental precursor. Typical growth temperature ranges between 300 and 700?C and pressure ranges between 1 and several hundred Torrs. We have studied the structural and the physical properties of GaAs, InGaAs, AlGaAs layers grown either on blanket or patterned Si(100) wafers by FIBSTEM, TEM, SIMS, ?PL, cathodoluminescence. We showed an improvement of the material quality as they are elaborated in SiO2 cavity even with an aspect ratio less than 2. Antiphase boundary and dislocation densities are strongly decreased as the width of the cavity goes bellow 100 nm. By adjusting properly the growth conditions and the stack in the quantum well structure, we were able to observe room temperature micro-photoluminescence of single InGaAs QW, with In composition ranging between 10 and 40%.

Resume : A successful monolithic integration of silicon CMOS with GaN-HEMTs by epitaxy requires the preservation of both kinds of device performances during the process. In the CMOS-first scenario, GaN is grown in defined areas of the Si substrate (Selective Area Growth, SAG), while existing CMOS areas are protected by a dielectric stack. However, the thermal budget of GaN growth is expected to strongly impact the CMOS characteristics. More, the thermal cycles involved in the epitaxy generate a severe stress on the protective dielectric layers above the CMOS, leading to a risk of delamination and CMOS devices damaging. It is therefore necessary to investigate in which extend the growth thermal budget could be reduced without penalty on the performances of GaN-HEMTs. In the present study, different structures were grown on Si by ammonia-MBE with standard and reduced thermal budgets, and then compared with regard to structural and electrical properties (AFM, SEM, XRD, C-V, Hall effect, and GaN transistors output characteristics). The study sets the limit for a trade-off between CMOS and GaN-HEMTs degradation. Based on these results, GaN SAG has been developed with a lower thermal budget (Tmax reduced from 920°C to 850°C). For this, a dielectric stack was designed in order to achieve the protection of the buried CMOS devices during the growth. The elaboration of low thermal budget GaN SAG brings us a step forward on the way to the monolithic integration of GaN-HEMTs with silicon CMOS.

Resume : Multiferroic materials are appealing for its application in microelectronic devices, but coexistence of ferroelectricity and ferromagnetism in a single material is generally restricted to low temperatures. Artificial multiferroics, combining ferroelectric (FE) and ferromagnetic (FM) phases are an alternative. High quality multiferroic FM/FE heterostructures can be fabricated on oxide single crystals, but its integration with silicon is elusive. We show here that high quality epitaxial CoFe2O4/BaTiO3 bilayer can be grown on buffered Si(001) by pulsed laser deposition. The use of a complex LaNiO3/CeO2/YSZ buffer layer is key to obtain epitaxy of BaTiO3 and CoFe2O4, and favour c-axis orientation of BaTiO3. Consequently, CoFe2O4/BaTiO3/LaNiO3/CeO2/YSZ heterostructures were deposited on Si(001) in a single process by pulsed laser deposition assisted with high energy electron diffraction (RHEED). Atomic force microscopy, X-ray diffractometry, and RHEED confirm high structural quality of the CoFe2O4/BaTiO3 heterostructures. CoFe2O4/BaTiO3 bilayers display good multiferroic properties, with high values of magnetization (> 200 emu/cm3) and polarization (>15 uC/cm2) at room temperature. Remarkably, the polarization of CFO/BTO bilayers is enhanced compared with bare BTO films and there are no fatigue up to more than 3xE9 cycles. Finally we show the influence of the CoFe2O4 on the ferroelectric polarization and current leakage of the BaTiO3 films.

Resume : Silicon based light emitting devices (LEDs) could enable fast, efficient, and power saving on-chip communication. Since bulk-Si (indirect band gap) is not suitable for any type of LED, Si nanocrystal (Si NC) based LEDs were proposed [1,2] due to their quasi direct gap and 5 orders of magnitude higher luminescence quantum yields. In order to fabricate a surface emitting Si NC device a transparent conductive oxide (TCO) deposition process without radiation or impact damage is mandatory to prevent deterioration of the quantum dots. We present Si NC LEDs fabricated by conventional sputtering of indium tin oxide (ITO) [3] and identify the damage caused by the sputtering-inherent and inevitable impact of accelerated heavy ions. For comparison we present a fabrication route based on low-impact thermal atomic layer deposition (ALD) of zinc oxide (ZnO). Zinc oxide is usually a n-type semiconductor based on hydrogen based defects and oxygen defects [4,5]. We show that the long term stability of the conductivity is limited which we attribute to the effusion of hydrogen even at ambient conditions. Therefore, we evaluate a method to encapsulate the hydrogen in the ZnO by an in-situ deposited ALD aluminum oxide (Al2O3) diffusion barrier. [1] K.Y. Cheng, et al., Nano Lett. 11, 1952 (2011) [2] R.J. Walters et al., Nature Mater. 4, 143 (2005) [3] J. Lopez-Vidrier et al., JAP 114, 163701 (2013) [4] Janotti et al., Nat mater 6, 2007 [5] Kim et al., Solid State Commun 152, 2012

Resume : InAs, InGaAs and GaAs nanocrystals (NCs) were fabricated by sequential ion implantation and flash lamp annealing. In detail, silicon-on-insulator (SOI) structures were provided with a SiO2 capping layer followed by the sequential implantation of In, Ga and As ions with fluences in the range of a few 1016 at./cm2. In order to get NCs at defined positions, in some cases ion implantation was performed through an additional, patterned Al capping layer. In the following step of flash lamp annealing the NCs will be formed in the Si device layer of the SOI wafer by liquid phase epitaxy. The resulting NCs are mostly single-crystalline with sizes of a few tens of nm. Transmission electron microscopy (TEM), Raman spectroscopy, atomic force microscopy (AFM), Rutherford Backscattering (RBS) and optical characterization are used to investigate the microstructure and the formation process of the NCs.

Resume : Ge1-xSnx is a material of interest for high performance logic and optoelectronic applications because of its high mobility and the fact that a direct band gap is predicted in the unstrained material for x exceeding ~ 0.1. Ge1-xSnx channel transistors have been investigated for CMOS applications. Metal/n-Ge contacts usually exhibit large specific contact resistivities as a result of Fermi level pinning at the interface, which in the case of MOSFETs degrades the device on-currents. This motivated us to investigate interface properties of metal/Ge1-xSnx contacts with respect to Sn percentage and metal work function. The Ge1-xSnx films with different Sn concentration were grown by molecular beam epitaxy (MBE). Transmission-line-measurement (TLM) structures and Schottky diodes were fabricated by structuring a mesa using reactive ion etching (RIE) followed by passivation with low temperature SiO2, structuring of contact holes and deposition of the respective metals. Schottky barrier heights and contact resistivities of Metal/Ge1-xSnx structure with different metal work functions and Sn concentrations were extracted from current ? voltage measurements and discussed.

Resume : The use of a lower band-gap material in the channel region of the MOSFET, such as SiGe, is a potential candidate given their compatibility with the process developed for pure Si-based devices. In addition, an increasing in the drain current and the transconductance due to the increased electrons mobility in SiGe material is expected. However, Bang gap narrowing due to Ge mole fraction increasing channel is critical problem that leads to electrical performance degradation. Therefore, in this paper we present a novel graded doping channel-based approach to improve the device reliability. Based on 2-D numerical investigation of a nanoscale SiGe Double Gate MOSFET including the defects in the interface region, in the present paper a numerical models for subthreshold characteristics by including the interfacial defects, after considering the uniform function approximation for the interface defects distribution at the drain said, are developed to explain the impact of the graded doping profile on the immunity behavior of the nanoscale transistor against the defect densities. In this context, subthreshold characteristics of the proposed design are analyzed by 2-D numerical simulation and compared with conventional uniform doping profile DG MOSFET characteristics.

Resume : A fabrication technique of metallic (Me) layers with a thickness of 2-15 microns which are strongly or weakly bound with a silicon (Si) wafer for Layer Transfer was developed. A managing adhesion of the Me layers was carried out by pre-formation of a copper/porous silicon (Cu/PS) sub- layer on the Si wafer. The Cu/PS layers were formed by anodizing the Si wafer and further Cu immersion deposition from a Cu sulfate and HF water solution. Than an electrochemical deposition was used to form Me layers. It was found that the Me layer transfer can go in 2 ways, depending on a PS porosity (p): (1) p<30% or p>85% - a separation of the Me layer occurs along its interface with PS; 30%85% Si crystallites of PS have an increased chemical resistance due to small sizes (<7 nm) and Cu ions from the immersion solution are unable to oxidize them and deposit in the pores. In the second case, an adhesion of the Me layers can be highly controlled in the range of 1.2-4.5 MPa by porosity variation. It should be noted that the Me layers which were deposited on a Cu-free PS showed a poor adhesion manageability. The developed technique is shown to be promising for the fabrication of interconnections between different wafers for MEMS (Probe Cards, Power Modules, etc).

Resume : The main challenge for Ge and SiGe layers integration into the low-cost near-infrared silicon based photodetectors is high absorption coefficient, long carriers lifetime and others. In the present work we studied the formation of multilayer struc-tures based on polycrystalline SiGe and Ge films, deposited at reduced pressure on silicon substrates. The low pressure hot wall horizontal reactor "Lada- 34" was used for the de-position of Ge, SiGe and a-Si cap layers at 500° C. The 0.5 and 1.0 um thick Ge films were used as the reference samples. Hydrogen high temperature processing was per-formed at 850°C using the epitaxial silicon chamber «Gemini-1". The structural properties of LPCVD grown thin Ge and SiGe films treated at hydrogen atmosphere has been investigated using Rutherford backscattering and scanning electronic microscopy methods. RBS and SEM analysis allowed to establish the structural properties and morpho-logical transformations is the Ge based structures. It is found that annealing in hydrogen enhances the mobility and diffusion of germanium atoms. This effect can be used to re-duce surface roughness of the structures using an optimized process regime. It is shown that maximum absorption at 1,3 µm wavelength is demonstrated for heterostructures based on Ge layers of 1.0 µm thick or higher.

Resume : Ceria (CeO2) attracted tremendous attention for diverse applications, such as catalysis, solid oxide fuel cells, and gas sensing, thanks to its high oxygen mobility as well as storage capacity. The origin of these promising abilities can be traced back to the presence of oxygen vacancies, causing a change in the crystallographic and electronic structure (Ce4+/Ce3+). Its neighboring rare earth oxide, praseodymia, shows opposite redox properties in terms of Pr valence state exchange (Pr4+/Pr3+) allowing to tailor the redox properties of mixed CePr oxide compounds. Thus, additional oxygen vacancies in Pr-doped CeO2 are created by a Pr4+/Pr3+ valence change in the CeO2 matrix, probably resulting in a strong local lattice distortion. Here, oxygen vacancy formation in single crystalline epitaxial Ce1-xPrxO2-δ (x = 0-1) thin films on Si(111) is studied by Raman spectroscopy in dependence on the Pr-concentration and temperature. The correlated global and local structure distortion was investigated by laboratory and synchrotron based X-ray diffraction (XRD) and extended X-ray absorption fine-structure (EXAFS) measurements, respectively. Furthermore, the valence states of Ce and Pr were explored by X-ray photoelectron spectroscopy (XPS). Concluding, it is found that we are able to tune oxygen vacancy concentration, oxygen storage capacity and oxidative capability by mixing Pr cations into the CeO2 fluorite lattice and identify the atomistic origin of these tailored redox properties.